Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9627387-B2
Application number	US-201514955078-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 4, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including active portions, each of the active portions including first and second dopant regions;
word lines on the substrate, the word lines extending in a first direction and intersecting the active portions;
first and second bit lines on the substrate, the first and second bit lines intersecting the word lines and extending in a second direction that is perpendicular to the first direction, the first and second bit lines being adjacent to each other and connected to the first dopant regions; and
contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view, the contact structures being in contact with the second dopant regions, respectively,
the contact structures each including a contact plug in contact with a portion of a contact pad, the contact pads of the contact structures contacting the second dopant regions,
the contact plugs being spaced apart from sidewalls of the first and second bit lines by a first distance between the first and second bit lines, each of the contact plugs having a bottom width that is less than a width of the contact pads, and
the contact pads being spaced apart from the sidewall of the first bit line by a second distance greater than the first distance and being adjacent to the sidewall of the second bit line.

2. The semiconductor device of claim 1 , further comprising:
a bit line contact pattern between each of the first dopant regions and each of the first bit lines;
a bit line contact spacer between the bit line contact pattern and the contact pad of one of the contact structures; and
a bit line spacer between the contact plug of one of the contact structures and the first and second bit lines on the bit line contact spacer.

3. The semiconductor device of claim 2 , wherein a width of the bit line contact spacer is greater than a width of the bit line spacer.

4. The semiconductor device of claim 2 , wherein widths of the bit line contact patterns are substantially equal to widths of the first and second bit lines.

5. The semiconductor device of claim 2 , wherein a bottom surface of the contact pad in one of the contact structures is lower than a top surface of the bit line contact spacer.

6. The semiconductor device of claim 2 , wherein the contact pad in one of the contact structures has a rounded sidewall adjacent to the bit line contact spacer when viewed from the plan view.

7. The semiconductor device of claim 1 , wherein an overlapping area between the contact pad in one of the contact structures and the active portion is greater than an overlapping area between the contact plug in one of the contact structures and the active portion when viewed from the plan view.

8. The semiconductor device of claim 1 , wherein a maximum distance between the contact pads adjacent to each other in the first direction is greater than a width of each of the first and second bit lines.

9. The semiconductor device of claim 1 , wherein
the portion of the contact pad is a first portion,
the contact pad includes a second portion opposite the first portion,
the second portion extends horizontally from a bottom of the contact plug, and
a thickness of the second portion is less than a thickness of the first portion.

10. A semiconductor device comprising:
a semiconductor substrate including active portions defined by a device isolation layer, each of the active portions including first and second dopant regions that are spaced apart from each other;
word lines on the substrate, the word lines extending in a first direction and intersecting the active portions;
bit line contact patterns connected to the first dopant regions between the word lines;
bit lines connected to the bit line contact patterns, the bit lines extending in a second direction perpendicular to the first direction to intersect the word lines;
contact pads on the substrate in regions between the word lines and between the bit lines when viewed from a plan view, the contact pads being in contact with the second dopant regions, respectively;
contact plugs electrically connected to the second dopant regions through the contact pads, each of the contact plugs having a bottom width that is less than a width of the contact pads;
bit line contact spacers on the substrate between the contact pads and the bit line contact patterns, each of the contact pads having a rounded sidewall adjacent to a corresponding one of the bit line contact spacers when viewed from a plan view; and
bit line spacers covering sidewalls of the bit lines and being in contact with top surfaces of the contact pads,
wherein each of the bit line contact patterns is between the contact pads adjacent to each other in the first direction.

11. The semiconductor device of claim 10 , wherein
the rounded sidewalls of adjacent contact pads among the contact pads face each other when viewed from the plan view, and
each of the bit line contact patterns between the rounded sidewalls of an adjacent pair of the contact pads.

12. The semiconductor device of claim 10 , wherein
the contact plugs are in contact with portions of the contact pads, respectively; and
the bit line spacers are between the bit lines and the contact plugs.

13. The semiconductor device of claim 12 , wherein a width of the bit line contact patterns is substantially equal to a width of the bit lines, and
a distance between the bit line contact patterns and adjacent contact pads among the contact pads is greater than a distance between the bit lines and adjacent contact plugs among the contact plugs.

14. The semiconductor device of claim 12 , wherein a bottom surface of the contact pads is lower than a top surface of the bit line contact spacers.

15. The semiconductor device of claim 12 , wherein a bottom surface of the bit line contact patterns is lower than a bottom surface of the contact pads.

16. The semiconductor device of claim 12 , wherein an overlapping area between the contact pads and the active portions is greater than an overlapping area between the contact plugs and the active portions when viewed from the plan view.

17. A semiconductor device comprising:
a semiconductor substrate including a trench that defines a plurality of active portions spaced apart from each other, each of the active portions including first and second dopant regions that are spaced apart from each other;
word lines on the substrate, the word lines intersecting the active portions and extending in a first direction, the word lines spaced apart from each other in a second direction crossing the first direction;
bit lines on the substrate, the bit lines extending in the second direction and being spaced apart from each other in the first direction,
bit line contact patterns spaced apart from each other, the bit line contact patterns electrically connecting the first dopant regions to the bit lines;
contact pads on top of the second dopant regions, each of the contact pads including a portion that extends from a side of a corresponding one of the second dopant regions towards an adjacent one of the bit line contact patterns and is spaced apart from the adjacent one of the bit line contact patterns; and
contact plugs electrically connected to the second dopant regions through the contact pads, each of the contact plugs having a bottom width that is less than a width of the contact pads, each of the contact plugs being on top of the portion of a corresponding one of the contact pads and on top of a corresponding

Assignees

• Jung Hyeonok
• Park Chan Ho
• Yoon Chan-Sic
• Lee Kiseok
• Lee Wonwoo
• Han Sunghee
• Samsung Electronics Co Ltd

Inventors

• Jung Hyeonok
• Park Chan Ho
• Yoon Chan-Sic
• Lee Kiseok
• Lee Wonwoo
• Han Sunghee

Classifications

• H01L27/10897

  Electricity · mapped topic

• H01L27/108 Primary

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic