Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9230612-B2
Application number	US-201314051841-A
Country	US
Kind code	B2
Filing date	Oct 11, 2013
Priority date	Oct 18, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of word lines extending in a first direction in or on a substrate;
a plurality of bit lines crossing over the plurality of word lines;
a plurality of bit line node contacts, each of the plurality of bit line node contacts connecting a corresponding bit line to the substrate, and each of the plurality of bit line node contacts having a width substantially equal to a width of the corresponding bit line;
a plurality of storage node contacts between the plurality of bit lines and connected to the substrate, a distance between a first sidewall of a first of the plurality of storage node contacts and a corresponding first bit line adjacent to the first sidewall is substantially equal to a distance between a second sidewall of the first storage node contact and a second bit line adjacent to the second sidewall; and
a plurality of storage node pads, each of the plurality of storage node pads being between the substrate and a corresponding storage node contact, each of the plurality of storage node pads having a width greater than a width of the corresponding storage node contact, and a sidewall of each of the plurality of storage node pads being aligned with a sidewall of the corresponding storage node contact.

2. The semiconductor device of claim 1 , wherein a sidewall of each of the plurality of bit line node contacts is aligned with a sidewall of the corresponding bit line.

3. The semiconductor device of claim 1 , wherein a distance between a first of the plurality of bit line node contacts and the first of the plurality of storage node contacts is substantially equal to a distance between the first of the plurality of storage node contacts and the corresponding first bit line.

4. The semiconductor device of claim 1 , further comprising:
a separation pattern between adjacent storage node pads, the separation pattern vertically overlapping with a corresponding bit line.

5. The semiconductor device of claim 1 , further comprising:
a buried insulation layer between the substrate and each bit line, a sidewall of the buried insulation layer being aligned with a sidewall of the corresponding storage node contact.

6. The semiconductor device of claim 1 , further comprising:
an insulation spacer between each bit line and corresponding storage node contact, and between each bit line node contact and corresponding storage node contact.

7. The semiconductor device of claim 6 , wherein the insulation spacer includes an air gap.

8. The semiconductor device of claim 1 , further comprising:
a data storage element electrically connected to the first of the plurality of storage node contacts.

9. A semiconductor device comprising:
at least two storage node contacts in or on a substrate;
a bit line node contact on the substrate between the at least two storage node contacts;
a bit line on the bit line node contact between the at least two storage node contacts, each of the bit line node contact and the bit line being spaced apart from sidewalls of the at least two storage node contacts by substantially the same distance; and
a storage node pad between the substrate and a first of the at least two storage node contacts, the storage node pad having a width greater than a width of the first of the at least two storage node contacts, and wherein a sidewall of the storage node pad is aligned with a sidewall of the first of the at least two storage node contacts.

10. The semiconductor device of claim 9 , wherein a sidewall of the bit line is vertically aligned with a sidewall of the bit line node contact.

11. The semiconductor device of claim 9 , further comprising:
an insulation spacer between the bit line and the first of the at least two storage node contacts and between the bit line node contact and the first of the at least two storage node contacts.

12. The semiconductor device of claim 11 , wherein the insulation spacer includes an air gap.

13. The semiconductor device of claim 9 , further comprising:
a data storage element electrically connected to the first of the at least two storage node contacts.

14. A semiconductor device comprising:
at least two storage node contacts in or on a substrate;
a bit line node contact in or on the substrate between the at least two storage node contacts;
a bit line on the bit line node contact between the at least two storage node contacts, the bit line node contact and the bit line being spaced apart from sidewalls of the at least two storage node contacts by a spacer; and
a storage node pad between the substrate and the at least two storage node contacts, the storage node pad having a width greater than a width of a first of the at least two storage node contacts, and a sidewall of the storage node pad being aligned with a sidewall of the first of the at least two storage node contacts.

15. The semiconductor device of claim 14 , wherein a sidewall of the bit line is aligned with a sidewall of the bit line node contact.

16. The semiconductor device of claim 14 , wherein a distance between the bit line node contact and the first of the at least two storage node contacts is substantially equal to a distance between the bit line and the first of the at least two storage node contacts.

17. The semiconductor device of claim 14 , further comprising:
a buried insulation layer between the bit line and the substrate, a sidewall of the buried insulation layer being aligned with a sidewall of the first of the at least two storage node contacts.

18. The semiconductor device of claim 14 , further comprising:
an insulation spacer between the bit line and the first of the at least two storage node contacts, and between the bit line node contact and the first of the at least two storage node contacts.

19. The semiconductor device of claim 18 , wherein the insulation spacer includes an air gap.

20. The semiconductor device of claim 14 , further comprising:
a data storage element electrically connected to the first of the at least two storage node contacts.

Assignees

• Park Jemin
• Samsung Electronics Co Ltd

Inventors

• Park Jemin

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B12/48 Primary

  Data lines or contacts therefor · CPC title

• H01L27/10888

  Electricity · mapped topic

• H01L27/10882

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic