Semiconductor devices having increased contact areas between contacts and active regions and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-8969936-B2
Application number	US-201213732344-A
Country	US
Kind code	B2
Filing date	Dec 31, 2012
Priority date	Mar 30, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a device isolation layer formed in a semiconductor substrate, the device isolation layer defining active regions each including a first junction region and a second junction region,
at least two adjacent word lines buried in the semiconductor substrate, the at least two adjacent word lines each having a word line capping layer formed thereon and extending above the active regions;
a plurality of bit lines extending across the at least two adjacent word lines;
first contacts electrically interconnecting the first junction region and a corresponding one of the plurality of bit lines;
second contacts, at least one of which is electrically coupled to a corresponding one of the second junction regions; and
a separation wall extending between at least two adjacent word line capping layers, the separation wall having a width less than a width of a corresponding bit line and located between adjacent second contacts, between adjacent first contacts, isolated from the adjacent first contacts, and under the corresponding bit line in plan view,
wherein a portion of at least one of the second contacts is disposed between sidewalls of adjacent word line capping layers.

2. The device of claim 1 , wherein at least one of the second contacts includes an upper portion and a lower portion, which are formed as a single integral body.

3. The device of claim 2 , wherein the device isolation layer has a top surface located lower than a top surface of the second junction region.

4. The device of claim 2 , wherein an area of the lower portion of the at least one of the second contacts overlapping with respect to the second junction region is greater than an area of the upper portion of the at least one of the second contacts overlapping with respect to the second junction region.

5. The device of claim 1 , wherein the device isolation layer has a top surface substantially planar with a top surface of the second junction region.

6. The device of claim 1 , wherein the separation wall extends along a direction crosswise of a direction of the at least two adjacent word lines.

7. The device of claim 1 , wherein the separation wall extends substantially parallel to a direction of the plurality of bit lines.

8. The device of claim 1 , wherein a material that forms the word line capping layer is substantially the same as a material that forms the separation wall.

9. The device of claim 1 , wherein the separation wall has a substantially line shape in plan view.

10. A semiconductor device comprising:
a device isolation layer formed in a semiconductor substrate, the device isolation layer defining an active region including a first junction region and a second junction region;
a plurality of word lines buried in the semiconductor substrate, the plurality of word lines each having a word line capping layer formed thereon and extending above the active region;
a plurality of bit lines extending across the plurality of word lines;
a first contact electrically interconnecting the first junction region and a corresponding one of the plurality of bit lines; and
a second contact electrically coupled to the second junction region,
wherein the second contact includes an upper portion and a lower portion, which are formed as a single integral body, and
wherein the lower portion of the second contact is disposed within a space confined by sidewalls of adjacent word line capping layers and sidewalls of adjacent separation walls extending between the adjacent word line capping layers, at least one of the separation walls having a width less than a width of a corresponding bit line and located isolated from the first contact and under the corresponding bit line in plan view.

11. The semiconductor device of claim 10 , wherein one of the adjacent separation walls is a contact spacer disposed adjacent a sidewall of the first contact.

12. The semiconductor device of claim 11 , wherein a height of the contact spacer is higher than a height of the adjacent separation walls.

13. The semiconductor device of claim 10 , wherein one of the sidewalls of the adjacent separation walls has a flat surface and another sidewall has a curved surface.

14. A semiconductor device comprising:
a device isolation layer formed in a semiconductor substrate, the device isolation layer defining an active region including a first junction region and a second junction region;
a plurality of word lines extending under a top surface of the semiconductor substrate, the plurality of word lines each having a word line capping layer formed thereon, the word line capping layers protruding above the active region;
a plurality of bit lines extending across the plurality of word lines;
an interlayer insulating layer disposed over the plurality of bit lines;
a first contact electrically interconnecting the first junction region and a corresponding one of the plurality of bit lines, the first contact disposed in a first contact hole defined in the interlayer insulating layer; and
a second contact electrically coupled to the second junction region, the second contact disposed in a second contact hole defined in the interlayer insulating layer,
wherein a lower portion of the second contact hole is confined by sidewalls of adjacent word line capping layers, by a sidewall of a separation wall extending between the adjacent word line capping layers and by a sidewall of a contact spacer disposed on a sidewall of the first contact hole, the separation wall having a width less than a width of a corresponding bit line and located isolated from the first contact and under the corresponding bit line in plan view, and
wherein the second contact includes an upper portion and a lower portion, which are formed as a single integral body.

15. The device of claim 14 , wherein a bottom surface of the second contact hole is substantially flat.

16. The device of claim 15 , wherein the bottom surface of the second contact hole is formed without a step.

17. The device of claim 14 , wherein a central vertical axis of the lower portion of the second contact is aligned with a central vertical axis of the upper portion of the second contact.

18. The device of claim 14 , wherein a central vertical axis of the lower portion of the second contact is offset from a central vertical axis of the upper portion of the second contact.

19. The device of claim 14 , wherein a top surface of the second junction region in contact with the second contact is substantially coplanar with a top surface of the device isolation layer underneath the separation wall.

20. The device of claim 14 , wherein a bottom of the separation wall is higher than a bottom of the contact spacer.

21. The device of claim 14 , wherein a height of the contact spacer is higher than a height of the separation wall.

22. The device of claim 14 , wherein at least one of the plurality of bit lines has a central vertical axis offset from a central vertical axis of the first contact.

23. The device of claim 14 , further comprising a capacitor electrically coupled to the second contact.

24. The device of claim 23 , wherein the capacitor includes a capacitor lower electrode coupled to a top surface of the second contact through a landing pad.

25. The device of claim 24 , wherein a central vertical axis of the landing pad is offset from a central vertical axis of the upper portion of the second contact.

Assignees

• Lee Wonchul
• Kim Eun A
• Lee Ja Young
• Samsung Electronics Co Ltd

Inventors

• Lee Wonchul
• Kim Eun A
• Lee Ja Young

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B12/488 Primary

  Word lines · CPC title