Thermal dissipation in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12451401-B2
Application number	US-202418583411-A
Country	US
Kind code	B2
Filing date	Feb 21, 2024
Priority date	Apr 28, 2020
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

First claim

What is claimed is:

1. A device comprising:
a layer of active devices;
a front-side interconnect structure on a front-side of the layer of active devices;
a backside interconnect structure on a backside of the layer of active devices, the backside interconnect structure comprising:
a first interconnect layer comprising a conductive line electrically connected to a source/drain region in the layer of active devices; and
a thermal dissipation path thermally connected to the layer of active devices, wherein the thermal dissipation path comprises a dummy via extending from a first metal line of the thermal dissipation path to a second metal line of the thermal dissipation path, wherein the front-side interconnect structure comprises a second thermal dissipation path thermally connected to the layer of active devices, wherein the second thermal dissipation path comprises a second dummy via extending from a third metal line of the second thermal dissipation path to a fourth metal line of the second thermal dissipation path.

2. The device according to claim 1 , wherein the backside interconnect structure comprises a passive device, and wherein the passive device comprises the first metal line and the second metal line.

3. The device according to claim 2 , wherein the passive device is a metal-insulator-metal (MIM) inductor.

4. The device according to claim 1 , wherein the first metal line, the second metal line, and the dummy via are electrically isolated from the layer of active devices.

5. The device according to claim 1 , wherein the third metal line, the fourth metal line, and the second dummy via are electrically isolated from the layer of active devices.

6. The device according to claim 1 , wherein the thermal dissipation path extends to a underbump metallization (UBM) structure at a surface of the backside interconnect structure that is opposite to the layer of active devices.

7. The device according to claim 1 , wherein the conductive line is a power line, and wherein the power line is thicker than the first metal line and the second metal line.

8. A device comprising:
a substrate;
a first interconnect structure over the substrate;
a device layer over the first interconnect structure, wherein the device layer comprises a first transistor;
a second interconnect structure over the device layer, the second interconnect structure comprising:
a conductive line electrically connected to a source/drain region of the first transistor;
a passive device; and
a dummy via in a first dielectric layer, the dummy via is thermally connected to the conductive line, wherein the dummy via extends from a first layer of the passive device to a second layer of the passive device.

9. The device according to claim 8 , wherein the passive device is a metal-insulator-metal (MIM) inductor.

10. The device according to claim 8 , wherein the conductive line is a power delivery line electrically connected to a backside of the source/drain region of the first transistor by a backside source/drain contact.

11. The device according to claim 8 , wherein the dummy via is disposed in a same layer as a functional via that is electrically connected to a second transistor in the device layer.

12. The device according to claim 11 , wherein the dummy via and the functional via are made of a same material.

13. The device according to claim 8 , wherein the first interconnect structure further comprises a second dummy via thermally connected to and electrically isolated from the first transistor.

14. The device according to claim 8 , wherein the substrate is directly bonded to the first interconnect structure by dielectric-to-dielectric bonds.

15. A device comprising:
a device layer comprising a transistor;
a first interconnect structure on a first side of the device layer, the first interconnect structure comprising a first source/drain contact electrically connected to a first source/drain region of the transistor; and
a second interconnect structure on a second side of the device layer opposite to the first interconnect structure, the second interconnect structure comprising:
a conductive line;
a second source/drain contact electrically connecting a second source/drain region of the transistor to the conductive line;
a dummy via thermally connecting the device layer to a surface of the second interconnect structure opposite to the device layer, wherein the dummy via is electrically isolated from the transistor; and
a metal-insulator-metal (MIM) inductor comprising a first metal component and a second metal component that overlaps the first metal component, wherein the dummy via extends from the first metal component to the second metal component.

16. The device according to claim 15 , wherein the first side of the device layer is a front-side of the device layer, and wherein the second side of the device layer is a backside of the device layer.

17. The device according to claim 15 , wherein the first interconnect structure further comprises a second dummy via thermally connecting the device layer to a surface of the first interconnect structure opposite to the device layer.

18. The device according to claim 17 , wherein the second dummy via is electrically isolated from the transistor.

19. The device according to claim 15 , wherein the dummy via extends continuously from a first dummy line in the second interconnect structure to a second dummy line in the second interconnect structure, and wherein the first dummy line and the second dummy line are electrically isolated from the transistor.

20. The device according to claim 15 , wherein the first source/drain contact extends to a first surface of the first source/drain region, wherein the second source/drain contact extends to a second surface of the second source/drain region, wherein the first surface of the first source/drain region is on the first side of the device layer, and wherein the second surface of the second source/drain region is on the second side of the device layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Wen-Sheh
• Chen Yu-Hsiang
• Chen Chii-Ping

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title