Semiconductor device including separate upper channel structures and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12439603-B2
Application number	US-202217690154-A
Country	US
Kind code	B2
Filing date	Mar 9, 2022
Priority date	Jul 14, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an electrode structure comprising electrodes stacked on a substrate, and an insulating pattern on an uppermost electrode of the electrodes;
a vertical structure that penetrates the electrode structure and is electrically connected to the substrate, the vertical structure comprising a vertical semiconductor pattern and a conductive pad on the vertical semiconductor pattern;
a first insulating layer on the electrode structure and the vertical structure, wherein the insulating pattern is between the first insulating layer and the uppermost electrode;
a capping pattern on the conductive pad between the first insulating layer and the conductive pad, the capping pattern comprising a different material than the first insulating layer;
a conductive pattern that penetrates the first insulating layer and the capping pattern, and is electrically connected to the vertical structure;
an upper horizontal electrode on the conductive pattern;
an upper separation pattern that crosses the upper horizontal electrode in a first direction; and
an upper semiconductor pattern that penetrates the upper horizontal electrode and is electrically connected to the conductive pattern,
wherein the conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern, and
the upper separation pattern is vertically overlapping with the vertical structure.

2. The semiconductor device of claim 1 , wherein a thickness of a first portion of the conductive pattern having the first side surface is greater than a thickness of a second portion of the conductive pattern having the second side surface, and an interface between the first and second portions of the conductive pattern comprises a step difference, and wherein the first insulating layer has etch selectivity with respect to the insulating pattern.

3. The semiconductor device of claim 1 , wherein the upper semiconductor pattern comprises a first portion, and a second portion that connects the first portion to the conductive pattern and has a width less than that of the first portion, and
the conductive pattern has a width greater than that of the second portion.

4. The semiconductor device of claim 1 , wherein a bottom end of the conductive pattern is closer to the substrate than a top surface of the insulating pattern.

5. The semiconductor device of claim 1 , wherein a height of the first side surface is greater than a thickness of the first insulating layer.

6. The semiconductor device of claim 5 , wherein the
capping pattern is directly on the conductive pad, and faces the first side surface, and
the conductive pattern extends through the first insulating layer and the capping pattern to directly contact the conductive pad.

7. The semiconductor device of claim 5 , wherein the
capping pattern is thinner than the first insulating layer, and the capping pattern has etch selectivity with respect to the first insulating layer.

8. The semiconductor device of claim 5 , wherein the upper horizontal electrode comprises a string selection line of a string selection transistor, and wherein the conductive pattern electrically connects the vertical structure to the string selection transistor.

9. The semiconductor device of claim 1 ,
wherein the conductive pattern has a width greater than a width of the upper separation pattern in a second direction perpendicular to the first direction.

10. The semiconductor device of claim 1 , wherein the vertical structure comprises a vertical insulating pattern on the vertical semiconductor pattern, and
a top surface of the conductive pad is closer to the substrate than a top surface of the vertical insulating pattern.

11. The semiconductor device of claim 1 , further comprising a second insulating layer between the first insulating layer and the upper horizontal electrode,
wherein the second insulating layer is on a portion of a top surface of the conductive pattern.

12. The semiconductor device of claim 1 , further comprising:
an upper conductive pad on the upper semiconductor pattern, and
bit lines electrically connected to the upper conductive pad.

13. A semiconductor device, comprising:
an electrode structure comprising electrodes and insulating patterns that are alternately stacked;
a pair of separation structures crossing the electrode structure and spaced apart from each other in a first direction;
a vertical structure between the pair of separation structures and penetrating the electrode structure, the vertical structure comprising a vertical semiconductor pattern and a conductive pad on the vertical semiconductor pattern;
a first insulating layer on the electrode structure and the vertical structure;
a capping pattern between the first insulating layer and the conductive pad, wherein the capping pattern is on the conductive pad, and the capping pattern comprises a different material than the first insulating layer;
a conductive pattern that penetrates the first insulating layer and the capping pattern and is electrically connected to the conductive pad;
a second insulating layer on the first insulating layer and the conductive pattern;
an upper horizontal electrode on the second insulating layer;
a pair of first upper separation patterns crossing the upper horizontal electrode in a second direction perpendicular to the first direction and vertically overlapping with the pair of separation structures;
a second upper separation pattern between the pair of first upper separation patterns and crossing the upper horizontal electrode in the second direction;
an upper channel structure that penetrates the upper horizontal electrode and the second insulating layer and is electrically connected to the conductive pad, the upper channel structure comprising an upper semiconductor pattern and an upper insulating pattern on the upper semiconductor pattern;
an interlayer insulating layer on the upper channel structure;
a bit line on the interlayer insulating layer; and
a contact plug that penetrates the interlayer insulating layer and electrically connects the bit line to the upper channel structure.

14. The semiconductor device of claim 13 , wherein the conductive pattern comprises a first portion having a first side surface on the conductive pad, and a second portion having a second side surface on an uppermost one of the insulating patterns, and
a thickness of the first portion is greater than a thickness of the second portion, and an interface between the first and second portions of the conductive pattern comprises a step difference.

15. The semiconductor device of claim 13 , wherein the upper semiconductor pattern comprises a first portion, and a second portion that connects the first portion to the conductive pattern and has a width less than that of the first portion, and
the conductive pattern has a width greater than that of the second portion.

16. The semiconductor device of claim 13 , wherein a bottom end of the conductive pattern is closer to the electrode structure than a top surface of the upper insulating pattern.

17. The semiconductor device of claim 13 , wherein a thickness of a largest portion of the conductive pattern is greater than a thickness of the first insulating layer.

18. The semiconductor device of claim 13 , wherein the upper horizontal electrode comprises a string selection line that is configured to select a memory cell string defined by the vertical structure.

19. An electronic system, comprising:
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Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Kim Jaeho
• Kim Joonsung
• Kim Jiwon
• Sung Sukkang
• Lee Sangdon
• Lee Jong-Min

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/40

  characterised by the peripheral circuit region · CPC title