Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Patent metadata

Field	Value
Publication number	US-10297610-B2
Application number	US-201715818061-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Jul 18, 2017
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction, wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion;
drain select gate electrodes laterally surrounding respective rows of drain select level assemblies; and
a drain select level isolation strip comprising at least one dielectric material and located between a neighboring pair of drain select gate electrodes;
wherein one of the drain select gate electrodes comprises:
a strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction; and
a plurality of cylindrical electrode portions that laterally surround a respective one of the drain select level channel portions;

wherein the drain select level isolation strip comprises a perforated dielectric strip portion including two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a subset of the drain select level assemblies that is arranged in two rows that extend along the first horizontal direction;
wherein the drain select level isolation strip directly contacts each of the drain select level channel portions that extend through the cylindrical openings in the drain select level isolation strip.

2. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction, wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion;
drain select gate electrodes laterally surrounding respective rows of drain select level assemblies; and
a drain select level isolation strip comprising at least one dielectric material and located between a neighboring pair of drain select gate electrodes;
wherein one of the drain select gate electrodes comprises:
a strip electrode portion including a pair of lengthwise sidewalls that generally extend along the first horizontal direction; and

a plurality of cylindrical electrode portions that laterally surround a respective one of the drain select level channel portions;
wherein the drain select level isolation strip comprises a perforated dielectric strip portion including two rows of cylindrical openings therethrough, wherein each of the cylindrical openings laterally surrounds a respective one of a subset of the drain select level assemblies that is arranged in two rows that extend along the first horizontal direction;
wherein the drain select level isolation strip further comprises a lower dielectric strip portion underlying the perforated dielectric strip portion and contacting sidewalls of a subset of the cylindrical electrode portions; and
wherein the lower dielectric strip portion comprises two lengthwise sidewalls, wherein each of the two lengthwise sidewalls of the lower dielectric strip portion comprises a respective alternating sequence of planar sidewall segments and concave sidewall segments.

3. The two-dimensional memory device of claim 2 , wherein each cylindrical electrode portion that laterally surrounds a drain select level channel portion within the subset of the drain select level assemblies contacts a respective concave sidewall segment of the lower dielectric strip portion.

4. The three-dimensional memory device of claim 2 , wherein the perforated dielectric strip portion comprises two lengthwise sidewalls, wherein each of the two lengthwise sidewalls of the perforated dielectric strip portion comprises a respective alternating sequence of planar sidewall segments and convex sidewall segments.

5. The three-dimensional memory device of claim 4 , wherein the planar sidewall segments of the perforated dielectric strip portion are vertically coincident with the planar sidewall segments of the lower dielectric strip portion.

6. The three-dimensional memory device of claim 2 , wherein the drain select level isolation strip further comprises an upper dielectric strip portion overlying the perforated dielectric strip portion, and having a pair of lengthwise sidewalls, wherein each of the pair of lengthwise sidewalls of the upper dielectric strip portion comprises a respective alternating sequence of planar sidewall segments and concave sidewall segments.

Assignees

• Sandisk Technologies Llc

Inventors

• Kai James
• Alsmeier Johann
• Yada Shinsuke
• Sai Akihisa
• Nagamine Sayako
• Orimoto Takashi
• Zhang Tong

Classifications

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title