Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10950622-B2
Application number	US-201916290456-A
Country	US
Kind code	B2
Filing date	Mar 1, 2019
Priority date	Sep 19, 2018
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A semiconductor memory device includes first conductive layers stacked and second conductive layers stacked in a first direction. The second conductive layers spaced from the first conductive layers in a second direction intersecting the first direction. A first memory pillar is between the first conductive layers and the second conductive layers in the second direction. The first memory pillar extends in the first direction and has a first length in the second direction. A second memory pillar is between the first conductive layers and the second conductive layers in the second direction. The second memory pillar is adjacent to the first memory pillar. The second memory pillar extends in the first direction and has a second length greater than the first length in the second direction.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of first conductive layers stacked in a first direction;
a plurality of second conductive layers stacked in the first direction and spaced from the plurality of first conductive layers in a second direction intersecting the first direction;
a first memory pillar between the plurality of first conductive layers and the plurality of second conductive layers in the second direction, the first memory pillar extending in the first direction, having a first length in the second direction, and including a first semiconductor layer extending in the first direction, a first charge storage film, between the first semiconductor layer and the plurality of first conductive layers, and a second charge storage film, between the first semiconductor layer and the plurality of second conductive layers; and
a second memory pillar between the plurality of first conductive layers and the plurality of second conductive layers in the second direction, the second memory pillar being adjacent to the first memory pillar, extending in the first direction, having a second length greater than the first length in the second direction, and including a second semiconductor layer extending in the first direction and a third charge storage film.

2. The semiconductor memory device according to claim 1 , wherein
the plurality of first conductive layers includes a first linear portion,
the plurality of second conductive layers includes a second linear portion, and
the first memory pillar is between the first linear portion and the second linear portion.

3. The semiconductor memory device according to claim 2 , wherein
the first linear portion and the second linear portion extend in a third direction intersecting the first direction and the second direction and
the first linear portion and the second linear portion are opposed to each other.

4. The semiconductor memory device according to claim 1 , wherein
the plurality of first conductive layers includes a first curved portion,
the plurality of second conductive layers includes a second curved portion, and
the second memory pillar is between the first curved portion and the second curved portion.

5. The semiconductor memory device according to claim 4 , wherein
the first curved portion and the second curved portion each have an arc shape.

6. The semiconductor memory device according to claim 1 , wherein
an outer circumference of a cross section, taken perpendicular to the first direction, of the first memory pillar has a rectangular shape, and
an outer circumference of a cross section, taken perpendicular to the first direction, of the second memory pillar has an elongated circular shape.

7. The semiconductor memory device according to claim 1 , wherein
an outer circumference of a cross section, taken perpendicular to the first direction, of the first semiconductor layer has a rectangular shape, and
an outer circumference of a cross section, taken perpendicular to the first direction, of the second semiconductor layer has an elongated circular shape.

8. The semiconductor memory device according to claim 1 , wherein
the first memory pillar and the second memory pillar each comprise a first silicon oxide film, a silicon nitride film, and a second silicon oxide film, which are sequentially provided from the plurality of first conductive layers.

9. The semiconductor memory device according to claim 1 , wherein
the first memory pillar and the second memory pillar each further include a block insulating film and a tunnel insulating film.

10. The semiconductor memory device according to claim 1 , further comprising:
a plurality of first memory pillars and a plurality of second memory pillars alternately arranged.

11. The semiconductor memory device according to claim 1 , wherein the third charge storage film surrounds the second semiconductor layer.

Assignees

• Toshiba Memory Corp

Inventors

• Kondo Masaki

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title