Three-dimensional memory device with on-axis self-aligned drain-select-level isolation structure and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10937800-B2
Application number	US-201916352157-A
Country	US
Kind code	B2
Filing date	Mar 13, 2019
Priority date	Mar 13, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack;
memory stack structures located within a respective one of the memory openings, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
a multi-pillared dielectric isolation structure comprising a plurality of dielectric pillar portions located within a respective one of the memory openings and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack and laterally separating laterally neighboring strips of at least one electrically conductive layer within the alternating stack.

2. The three-dimensional memory device of claim 1 , wherein an entirety of the multi-pillared dielectric isolation structure is a structure of integral construction and has a homogeneous composition throughout.

3. The three-dimensional memory device of claim 1 , wherein each of the vertical semiconductor channels comprises:
a tubular semiconductor channel portion including a top surface that contacts a bottom surface of a respective one of the plurality of dielectric pillar portions; and
a semitubular semiconductor channel portion adjoined to an upper end of the tubular semiconductor channel portion and contacting sidewalls of the respective one of the plurality of dielectric pillar portions.

4. The three-dimensional memory device of claim 3 , further comprising drain regions contacting a respective one of the semitubular semiconductor channel portions and having a cylindrical drain segment and a block arc drain segment.

5. The three-dimensional memory device of claim 4 , wherein the plurality of dielectric pillar portions contacts bottom surfaces of the drain regions.

6. The three-dimensional memory device of claim 3 , wherein each of the memory films comprises:
a tubular memory film portion including a top surface that contacts a bottom surface of one of the plurality of dielectric pillar portions; and
a semitubular memory film portion adjoined to an upper end of the tubular memory film portion and contacting sidewalls of the one of the plurality of dielectric pillar portions.

7. The three-dimensional memory device of claim 3 , further comprising:
dielectric liners located within the memory openings and contacting a sidewall of a respective one of the semitubular semiconductor channel portions and a sidewall of a respective one of the plurality of dielectric pillar portions; and
dielectric cores located within the memory openings, contacting a bottom surface of a respective one of the plurality of dielectric pillar portions, and laterally surrounded by a respective one of the tubular semiconductor channel portions.

8. The three-dimensional memory device of claim 1 , wherein dielectric pillar portions within the plurality of dielectric pillar portions are laterally spaced from each other by one of the insulating layers within the alternating stack, wherein the one of the insulating layers laterally encircles and encloses each of the memory openings.

9. The three-dimensional memory device of claim 1 , wherein each of the memory openings includes one of the plurality of dielectric pillar portions and one of the memory stack structures.

10. The three-dimensional memory device of claim 1 , wherein each of the plurality of dielectric pillar portions comprises:
a cylindrical dielectric pillar portion centered at a vertical axis passing through a geometrical center of a respective one of the memory openings and azimuthally extending around the vertical axis by 360 degrees; and
a block arc pillar portion centered at the vertical axis, adjoined to one side of the cylindrical dielectric pillar portion, and azimuthally extending around the vertical axis by an angle in a range from 30 degrees to 270 degrees.

11. The three-dimensional memory device of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

12. The three-dimensional memory device of claim 11 , further comprising a backside blocking dielectric layer disposed between each neighboring pair of an electrically conductive layer and an insulating layer and extending from a bottommost layer within the alternating stack to a topmost layer within the alternating stack, wherein pedestal channel portions underlying a respective one of the vertical semiconductor channels are laterally spaced from the backside blocking dielectric layer by tubular dielectric spacers.

13. The three-dimensional memory device of claim 1 , wherein the at least one horizontally-extending portion comprises a plurality of horizontally-extending portions that laterally extend along a first horizontal direction, contact a top surface of an underlying one of the insulating layers within the alternating stack and contact a bottom surface of an overlying one of the insulating layers within the alternating stack.

14. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory openings vertically extending through the alternating stack;
forming memory stack structures within the memory openings, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel having a cylindrical configuration;
forming discrete corner cavities by removing an upper corner portion of each memory stack structure within two neighboring rows of memory openings using at least one etch process;
forming at least one laterally-extending cavity by laterally recessing portions of the electrically conductive layers from the discrete corner cavities; and
forming a multi-pillared dielectric isolation structure by depositing a dielectric material in volumes of the at least one laterally-extending cavity and in the discrete corner cavities.

15. The method of claim 14 , further comprising:
forming a patterned etch mask layer including an elongated opening over the memory stack structures and the alternating stack, wherein straight edges of the elongated opening overlie the two neighboring rows of memory openings;
etching portions of the vertical semiconductor channels that underlie the elongated opening in the patterned etch mask layer; and
etching portions of the memory films adjacent to cavities formed by etching portions of the vertical semiconductor channels, wherein the discrete corner cavities are formed within the two neighboring rows of memory openings.

16. The method of claim 14 , further comprising performing an isotropic etch process that uses an etchant that etches a material of the electrically conductive layers selective

Assignees

• Sandisk Technologies Llc

Inventors

• Kim Tae-Kyung
• Alsmeier Johann

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title