Transistor DV/DT control circuit

Patent metadata

Field	Value
Publication number	US-12438528-B2
Application number	US-202318513456-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Jun 30, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

First claim

What is claimed is:

1. A circuit comprising:
a first switch having a first gate terminal, a first source terminal and a first drain terminal;
a sense circuit coupled to the first drain terminal and arranged to generate a signal in response to sensing a voltage at the first drain terminal; and
a control circuit coupled to the first gate terminal and arranged to change a voltage at the first gate terminal in response to receiving the signal, wherein the voltage at the first gate terminal is changed at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage,
wherein the second intermediate voltage is lower than the first intermediate voltage; and
wherein the voltage at the first gate terminal is further changed from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, and wherein the first rate of voltage with respect to time is higher than the second rate of voltage with respect to time.

2. The circuit of claim 1 , further comprising a current mirror circuit coupled to the sense circuit.

3. The circuit of claim 2 , wherein the control circuit is coupled to the current mirror circuit.

4. The circuit of claim 1 , wherein the first rate of voltage with respect to time is higher than the second rate of voltage with respect to time.

5. The circuit of claim 1 , wherein the third rate of voltage with respect to time is higher than the second rate of voltage with respect to time.

6. The circuit of claim 1 , wherein the control circuit comprises a second switch having a second gate terminal, a second drain terminal and a second source terminal, and wherein the second drain terminal is coupled to the first gate terminal.

7. The circuit of claim 6 , wherein the control circuit is arranged to cause the second switch to discharge the first gate terminal such that the voltage at the first gate terminal is changed at the first rate of voltage with respect to time from the first voltage to the first intermediate voltage, and at the second rate of voltage with respect to time from the first intermediate voltage to the second intermediate voltage.

8. The circuit of claim 6 , wherein the control circuit further comprises a third switch having a third gate terminal, a third drain terminal and a third source terminal, and wherein the third drain terminal is coupled to the first gate terminal.

9. The circuit of claim 8 , wherein the third switch is a pull-down switch.

10. A circuit comprising:
a first switch having a first gate terminal, a first source terminal and a first drain terminal;
a sense circuit coupled to the first drain terminal and arranged to generate a signal in response to sensing a voltage at the first drain terminal; and
a control circuit coupled to the first gate terminal and arranged, in response to receiving the signal, to allow a discharge current to flow from the first gate terminal at a first current rate during a first time period, and to allow the discharge current to flow from the first gate terminal at a second current rate during a second time period; and
a current mirror circuit coupled to the sense circuit.

11. The circuit of claim 10 , wherein the control circuit is further arranged to allow the discharge current to flow from the first gate terminal at a third current rate during a third time period.

12. The circuit of claim 10 , wherein the first current rate is higher than the second current rate.

13. The circuit of claim 11 , wherein the third current rate is higher than the second current rate.

14. The circuit of claim 10 , wherein the control circuit is further arranged to allow the discharge current to flow from the first gate terminal at the first current rate during a third time period.

15. The circuit of claim 14 , wherein the control circuit comprises a second switch having a second gate terminal, a second drain terminal and a second source terminal, wherein the second drain terminal is coupled to the first gate terminal and wherein the second switch is arranged to allow the discharge current to flow at the first current rate.

16. The circuit of claim 15 , wherein the control circuit further comprises a third switch having a third gate terminal, a third drain terminal and a third source terminal, and wherein the third drain terminal is coupled to the first gate terminal, wherein the second and third switches are arranged, in combination, to allow the discharge current to flow at the first current rate and at the second current rate.

17. The circuit of claim 10 , wherein the control circuit is coupled to the current mirror circuit.

18. A method operating a circuit, the method comprising:
providing a first switch having a first gate terminal, a first source terminal and a first drain terminal;
providing a sense circuit coupled to the first drain terminal;
providing a current mirror circuit coupled to the sense circuit;
detecting, by the sense circuit, a voltage at the first drain terminal;
generating, by the sense circuit, a signal corresponding to the detected voltage at the first drain terminal;
receiving, by a control circuit coupled to the first gate terminal, the signal;
in response to receiving the signal, allowing a discharge current to flow from the first gate terminal at a first current rate during a first time period, allowing the discharge current to flow from the first gate terminal at a second current rate during a second time period, and allowing the discharge current to flow from the first gate terminal at a third current rate during a third time period; and
wherein the first current rate is higher than the second current rate and the first current rate is equal to the third current rate.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Jia Hongwei
• Sharma Santosh
• Kinzer Daniel M
• Sinow Victor
• Topp Matthew Anthony

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title