Gate driving circuit and method for driving semiconductor device

Patent metadata

Field	Value
Publication number	US-9543928-B2
Application number	US-18931908-A
Country	US
Kind code	B2
Filing date	Aug 11, 2008
Priority date	Aug 27, 2007
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A gate driving circuit and method can improve the tradeoff relation between the noise and the loss caused in the turn-OFF switching of semiconductor device. The gate driving circuit includes first and second series circuits. The first series circuit includes first and second MOSFETs connected in series. The gate terminal of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of the second MOSFET. The emitter of the semiconductor device is connected to the negative potential side of the second MOSFET or a DC power source. The second series circuit includes a capacitor and a third MOSFET connected in series. The second series circuit is connected in parallel with the second MOSFET. The semiconductor device is turned OFF by turning ON the second and third MOSFETs and turning OFF the first MOSFET.

First claim

What is claimed is:

1. A gate driving circuit for controllably turning ON and OFF a semiconductor device having a gate and an emitter, the gate driving circuit comprising:
a first series circuit having a first MOSFET and a second MOSFET connected in series with the first MOSFET;
a second series circuit having a capacitor and a third MOSFET connected in series with the capacitor;
a fourth MOSFET connected in parallel with the second MOSFET,
wherein the first series circuit configured to be connected to a positive side and a negative side of a DC power supply,
wherein the second series circuit is connected in parallel with the second MOSFET,
wherein the gate of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of each of the second, third, and fourth MOSFETs, and the emitter of the semiconductor device is connected to a negative potential side of each of the second, third, and fourth MOSFETs,
wherein a common ON/OFF activating signal is concurrently input to both the second and third MOSFETs to turn ON/OFF both the second and third MOSFETs,
wherein turning OFF the first MOSFET and turning ON the second and third MOSFETs turn OFF the semiconductor device,
wherein the fourth MOSFET is turned ON as the semiconductor device is brought into an OFF state to keep the semiconductor device in the OFF state,
wherein the third MOSFET is always turned ON, from an OFF-state, before turning ON the second MOSFET to draw charges accumulated between the gate and the emitter of the semiconductor device into the capacitor, each time the semiconductor device is switched OFF,
wherein at least one of the gate resistance or the ON-state resistance of the second MOSFET is higher than the corresponding gate resistance or the ON-state resistance of the third MOSFET to turn ON the third MOSFET before turning ON the second MOSFET,
wherein the second series circuit prevents turn-OFF noise and turn-OFF loss of the semiconductor device, and
wherein the second series circuit increases a change rate dv/dt of a voltage Vce when Vce<Vdc, Vdc being a DC voltage, while the change rate dv/dt of the voltage Vce remains substantially the same when Vce>Vdc, relative to when the gate driving circuit omits the second series circuit.

2. The gate driving circuit according to claim 1 , wherein the emitter of the semiconductor device is connected to the negative potential side of the DC power supply.

3. The gate driving circuit according to claim 1 , wherein the ON-state resistance of the second MOSFET is higher than the ON-state resistance of the third MOSFET to turn on the third MOSFET before turning ON the second MOSFET.

4. The gate driving circuit according to claim 1 , wherein:
the ON-state resistance of the second MOSFET is higher than the ON-state resistance of the third MOSFET to turn on the third MOSFET before turning ON the second MOSFET, and
the ON-state resistance of the second MOSFET is also higher than the ON-state resistance of the fourth MOSFET.

5. The gate driving circuit according to claim 1 , wherein the ON-state resistance of the fourth MOSFET is lower than the ON-state resistance of the second MOSFET and the ON-state resistance of the third MOSFET.

6. The gate driving circuit according to claim 3 , wherein the channel length in the second MOSFET is longer than the channel length in the third MOSFET to have the ON-state resistance of the second MOSFET be higher than the ON-state resistance of the third MOSFET.

7. A gate driving circuit for controllably turning ON and OFF a semiconductor device having a gate and an emitter, the gate driving circuit comprising:
a first series circuit having a first MOSFET and a second MOSFET connected in series with the first MOSFET;
a second series circuit having a capacitor and a third MOSFET connected in series with the capacitor;
a fourth MOSFET connected in parallel with the second MOSFET,
wherein the first series circuit configured to be connected to a positive side and a negative side of a DC power supply,
wherein the second series circuit is connected in parallel with the second MOSFET,
wherein the gate of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of each of the second, third, and fourth MOSFETs, and the emitter of the semiconductor device is connected to a negative potential side of each of the second, third, and fourth MOSFETs,
wherein a common ON/OFF activating signal is concurrently input to both the second and third MOSFETs to turn ON/OFF both the second and third MOSFETs,
wherein turning OFF the first MOSFET and turning ON the second and third MOSFETs turn OFF the semiconductor device,
wherein the fourth MOSFET is turned ON as the semiconductor device is brought into an OFF state to keep the semiconductor device in the OFF state,
wherein the second and third MOSFETs are turned ON simultaneously,
wherein the third MOSFET is always turned ON, from an OFF-state, to draw charges accumulated between the gate and the emitter of the semiconductor device into the capacitor, each time the semiconductor device is switched off,
wherein the second series circuit prevents turn-OFF noise and turn-OFF loss of the semiconductor device, and
wherein the second series circuit increases a change rate dv/dt of a voltage Vce when Vce<Vdc, Vdc being a DC voltage, while the change rate dv/dt of the voltage Vce remains substantially the same when Vce>Vdc, relative to when the gate driving circuit omits the second series circuit.

Assignees

• Yamashiro Keisuke
• Takubo Hiromu
• Fuji Electric Co Ltd

Inventors

• Yamashiro Keisuke
• Takubo Hiromu

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K17/168 Primary

  in composite switches · CPC title