Gate driver circuit

Patent metadata

Field	Value
Publication number	US-9300285-B2
Application number	US-201414198255-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Dec 18, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A gate driver circuit may include a driving signal generating unit generating first and second control signals based on a data signal and a fault state signal and controlling gate detection, a driving inverter operating in response to the first and second control signals to generate a gate signal and providing the gate signal to a power switch element, and a soft turn-off/gate detecting unit operating in response to the second control signal, performing a soft turn-off in the case of a fault, and detecting the gate signal to provide a detected signal.

First claim

What is claimed is:

1. A gate driver circuit, comprising:
a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;
a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element; and
a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal;
wherein the first control signal has a level into which the data signal is inverted when the fault state signal is at the low level and has a level into which the fault state signal is inverted regardless of a level of the data signal when the fault state signal is at the high level,
wherein the second control signal has a same level as the first control signal when the fault state signal is at the low level and has a level of the fault state signal regardless of the level of the first control signal when the fault state signal is at the high level.

2. The gate driver circuit of claim 1 , wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.

3. The gate driver circuit of claim 1 , wherein the driving signal generating unit includes:
a first inverter inverting the data signal;
a second inverter inverting the fault state signal;
an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;
a first buffer providing the first control signal to the driving inverter;
an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; and
a second buffer providing the second control signal to the soft turn-off/gate detecting unit.

4. The gate driver circuit of claim 1 , wherein the driving inverter includes:
a level shifter shifting a level of the second control signal;
a PMOS transistor having a source connected to an operating voltage terminal, a gate connected to an output terminal of the level shifter, and a drain; and
an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate receiving the first control signal, and a source connected to a ground,
wherein the gate signal is provided from a connection node between the PMOS transistor and the NMOS transistor via a resistor.

5. The gate driver circuit of claim 1 , wherein the soft turn-off/gate detecting unit includes:
an NMOS transistor having a drain connected to a gate of the power switch element, a gate receiving the second control signal, and a source; and
a detecting resistor connected between the source of the NMOS transistor and a ground and proportionally detecting a gate voltage of the power switch element to provide the detected signal.

6. A gate driver circuit, comprising:
a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;
a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element;
a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal;
a clamp controlling unit configured to provide a gate clamp control signal based on the second control signal and the detected signal; and
an active clamp circuit unit configured to operate in response to the clamp control signal of the clamp controlling unit to connect a gate of the power switch element to a ground;
wherein the first control signal has a level into which the data signal is inverted when the fault state signal is at the low level and has a level into which the fault state signal is inverted regardless of a level of the data signal when the fault state signal is at the high level,
wherein the second control signal has a same level as the first control signal when the fault state signal is at the low level and has a level of the fault state signal regardless of the level of the first control signal when the fault state signal is at the high level.

7. The gate driver circuit of claim 6 , wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.

8. The gate driver circuit of claim 6 , wherein the driving signal generating unit includes:
a first inverter inverting the data signal;
a second inverter inverting the fault state signal;
an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;
a first buffer providing the first control signal to the driving inverter;
an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; and
a second buffer providing the second control signal to the soft turn-off/gate detecting unit.

9. The gate driver circuit of claim 6 , wherein the driving inverter includes:
a level shifter shifting a level of the second control signal;
a PMOS transistor having a source connected to an operating voltage terminal, a gate connected to an output terminal of the level shifter, and a drain; and
an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate receiving the first control signal, and a source connected to a ground,
wherein the gate signal is provided from a connection node between the PMOS transistor and the NMOS transistor via a resistor.

10. The gate driver circuit of claim 6 , wherein the soft turn-off/gate detecting unit includes:
an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the second control signal, and a source; and
a detecting resistor connected between the source of the NMOS transistor and a ground and proportionally detecting a gate voltage of the power switch element to provide the detected signal.

11. The gate driver circuit of claim 6 , wherein the clamp controlling unit includes:
an inverter inverting the detected signal;
an AND gate performing an AND operation on the second control signal and an output signal of the inverter; and
a buffer providing an output signal of the AND gate to the active clamp circuit unit as the clamp control signal.

12. The gate driver circuit of claim 6 , wherein the active clamp circuit unit includes an NMOS transistor having a drain connected to the gate of the power switch element, a gate receiving the clamp control signal, and a source connected to the ground.

13. A gate driver circuit, comprising:
a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;
a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element;
a soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect t

Assignees

• Samsung Electro Mech

Inventors

• Pang Sung Man

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L29/78

  Electricity · mapped topic

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K17/163

  Soft switching · CPC title

• H03K17/28 Primary

  Modifications for introducing a time delay before switching (modifications to provide a choice of time-intervals for executing more than one switching action H03K17/296) · CPC title