Systems and methods for test circuitry for insulated-gate bipolar transistors

Patent metadata

Field	Value
Publication number	US-9588170-B2
Application number	US-201414341269-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Jul 25, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”) includes a first input operable to receive an on signal, a second input coupled to an IGBT driver circuit, and an output coupled to a control electrode of the IGBT. The output indicates a change in a state of a saturation voltage associated with the IGBT during operation of the IGBT.

First claim

What is claimed is:

1. A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”), the circuit comprising:
a first input operable to receive an on signal;
a second input coupled to an IGBT driver circuit; and
an output coupled to a control electrode of the IGBT, the output operable to indicate a change in a state of a saturation voltage associated with the IGBT during operation of the IGBT;
a first latch having a first input coupled to a supply voltage and a second input coupled to an output of a comparator, the comparator being part of the IGBT driver circuit;
a second latch having a first input coupled to an output of the first latch, and a second input operable to receive a delayed on signal.

2. The circuit of claim 1 , wherein the first latch is a D flip-flop.

3. The circuit of claim 1 , wherein the second latch is a D flip-flop.

4. The circuit of claim 1 , wherein the output is to indicate the change in the state of the saturation voltage by means of a logical operation of the on signal and the delayed on signal.

5. The circuit of claim 1 , wherein the first latch further comprises a reset input coupled to a pulse module.

6. The circuit of claim 1 , wherein the delayed on signal is an inverted, delayed variant of the on signal.

7. The circuit of claim 1 , wherein the saturation edge detection circuit further comprises an inverter having an input operable to receive the on signal.

8. The circuit of claim 7 , wherein the saturation edge detection circuit further comprises a delay module having an input coupled to an output of the inverter and an output operable to provide the delayed on signal.

9. The circuit of claim 1 , wherein the saturation edge detection circuit further comprises a pulse module having an input operable to receive the on signal and an output coupled to a reset input of the first latch.

10. The circuit of claim 1 , wherein the saturation edge detection circuit further comprises an OR gate having a first input coupled to the on signal, and a second input coupled to an output of the second latch.

11. The circuit of claim 10 , wherein the saturation edge detection circuit further comprises an AND gate having a first input coupled to an output of the OR gate, a second input operable to receive the on signal, and an output coupled to the control electrode of the IGBT.

12. The circuit of claim 1 , wherein the first latch is a D flip-flop and the second input of the first latch is a clock input, and wherein the second latch is a D flip-flop and the second input of the second latch is a clock input.

13. A method for testing a saturation level in an insulated gate bipolar transistor (“IGBT”), the method comprising:
receiving an on signal;
receiving a signal indicating whether a voltage level at a test saturation node of an IGBT driver circuit is above a threshold voltage;
storing a state associated with the voltage level;
storing information associated with a change in the voltage level;
performing a logical operation with the state associated with the voltage level and the information associated with the change in the voltage level; and
in response to the logical operation, lowering a control voltage on a control electrode of the IGBT.

14. The circuit of claim 13 , wherein storing a state associated with the voltage level is performed by a D flip-flop.

15. The circuit of claim 14 , wherein the D flip-flop comprises a reset input coupled to a pulse module.

16. The circuit of claim 15 , wherein the D flip-flop comprises an input coupled to a supply voltage.

17. The circuit of claim 15 , wherein the D flip-flop comprises an input coupled to the IGBT driver circuit.

18. The circuit of claim 13 , wherein storing information associated with the change in the voltage level is performed by a D flip-flop.

19. The circuit of claim 18 , wherein the D flip-flop comprises a clock input coupled a delayed variant of the on signal.

20. The circuit of claim 19 , wherein the delayed variant of the on signal is an inverted, delayed variant of the on signal.

Assignees

• Sicard Thierry
• Nxp Usa Inc

Inventors

• Sicard Thierry

Classifications

• H03K17/0822

  in field-effect transistor switches · CPC title

• G01R31/2608 Primary

  for testing bipolar transistors · CPC title

• H01L29/7393

  Electricity · mapped topic

• G01R35/00

  Testing or calibrating of apparatus covered by the other groups of this subclass · CPC title

• H03K2217/0027

  Measuring means of, e.g. currents through or voltages across the switch · CPC title