Systems and methods for testing a clamp function for insulated gate bipolar transistors

Patent metadata

Field	Value
Publication number	US-9720030-B2
Application number	US-201514733589-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	Jun 8, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An integrated circuit includes an insulated gate bipolar transistor (“IGBT”), a clamp element coupled to a control gate of the IGBT to allow current flow in a first direction when voltage is applied to the control gate of the IGBT, and a blocking element coupled to the control gate of the IGBT and to the clamp element. The blocking element allows current flow in a second direction when voltage is removed from the control gate of the IGBT, the second direction is opposite the first direction. A resistive element has a first terminal and a second terminal, the first terminal is coupled between an anode of the clamping element and an anode of the blocking element and the second terminal is coupled to an output of test circuitry.

First claim

What is claimed is:

1. An integrated circuit comprising:
an insulated gate bipolar transistor (“IGBT”);
a clamp element coupled to a control gate of the IGBT to allow current flow in a first direction when voltage is applied to the control gate of the IGBT;
a blocking element coupled to the control gate of the IGBT and to the clamp element, the blocking element allows current flow in a second direction when voltage is removed from the control gate of the IGBT, the second direction is opposite the first direction;
a resistive element having a first terminal and a second terminal, the first terminal is coupled between an anode of the clamping element and an anode of the blocking element and the second terminal is coupled to an output of test circuitry;
a collector-emitter voltage (VCE) detection circuit including:
a voltage detector coupled between an output of a PMOS current mirror and a supply voltage, the voltage detector including a first resistive element and a second resistive element coupled in series, wherein a first terminal of the first resistive element is coupled to the output of the PMOS current mirror and a terminal of the second resistive element is coupled to the supply voltage;
a comparator having a first input coupled to the voltage detector, a second input coupled to a reference voltage, and an output indicating whether the collector-emitter voltage is above the reference voltage.

2. The integrated circuit of claim 1 , wherein the clamp element is a Zener diode having an anode and a cathode and the blocking element is a blocking diode having an anode and a cathode, wherein the cathode of the Zener diode is coupled to a voltage source, the anode of the Zener diode is coupled to the anode of the blocking diode, and the cathode of the blocking diode is coupled to the control gate of the IGBT.

3. The integrated circuit of claim 1 , wherein:
when the integrated circuit transitions from on to off, the output of the test circuitry is a voltage that is less than a voltage at the control gate of the IGBT to enable current to flow through the clamp element; and
when the integrated circuit transitions from off to on, the voltage output by the test circuitry is greater than the voltage at the control gate of the IGBT to enable current to flow through the blocking element.

4. The integrated circuit of claim 3 , wherein the test circuitry further comprises:
a clamp test circuit including:
a comparator having a first input coupled to a reference voltage;
a PMOS current mirror coupled to the output of the test circuitry;
an NMOS current mirror having a first input coupled to the PMOS current mirror, a second input coupled to a current source, and an output coupled to a second input of the comparator;
the comparator outputs a signal indicating current is flowing through the clamp element in the first direction.

5. The integrated circuit of claim 4 , wherein the clamp test circuit further comprises:
a first flip-flop circuit having a data input coupled to the signal output by the comparator, an enable input coupled to an inverted ON/OFF signal and an output indicating proper operation through the clamp element.

6. The integrated circuit of claim 5 , wherein the clamp test circuit further comprises:
a second flip-flop circuit having a data input coupled to the signal output by the comparator, an enable input coupled to a non-inverted ON/OFF signal and an output indicating proper operation through the blocking element.

7. The integrated circuit of claim 6 , further comprising a gate driver circuit coupled to the control gate of the IGBT.

8. The integrated circuit of claim 6 , further comprising a logic gate including a first input coupled to the output of the first flip-flop circuit, a second input coupled to the output of the second flip-flop circuit, and an output indicating proper operation of both the clamp element and the blocking element.

9. The integrated circuit of claim 6 , wherein the maximum voltage of the clamping element is greater than the maximum collector-emitter voltage of the IGBT.

10. An integrated circuit comprising:
an insulated gate bipolar transistor (“IGBT”);
a clamp element coupled to a control gate of the IGBT to allow current flow in a first direction when voltage is applied to the control gate of the IGBT;
a blocking element coupled to the control gate of the IGBT and to the clamp element, the blocking element allows current flow in a second direction when voltage is removed from the control gate of the IGBT, the second direction is opposite the first direction;
a first resistive element;
a second resistive element having a first terminal coupled to an anode of the clamp element and a second terminal coupled to an anode of the blocking element;
a clamp test circuit having an output coupled to a first terminal of the first resistive element, wherein a second terminal of the first resistive element is coupled between the anode of the clamp element and the first terminal of the second resistive element; and
a collector-emitter voltage (VCE) detection circuit including an output coupled to the first terminal of the first resistive element, the output indicating whether a collector-emitter voltage of the IGBT is greater than a specified value, wherein the VCE detection circuit includes:
a voltage detector coupled between an output of a PMOS current mirror and a supply voltage, wherein the voltage detector includes a first resistive element and a second resistive element coupled in series, wherein a first terminal of the first resistive element is coupled to the output of the PMOS current mirror and a terminal of the second resistive element is coupled to the supply voltage;
a comparator having a first input coupled to the voltage detector, a second input coupled to a reference voltage, and the output indicating whether the collector-emitter voltage is greater than the specified value.

11. The integrated circuit of claim 10 , wherein the cathode of the clamp element is coupled to a collector of the IGBT and to a voltage source.

12. The integrated circuit of claim 10 , wherein the clamp test circuit includes:
a comparator having a first input coupled to a reference voltage;
a PMOS current mirror coupled to the output of the test circuitry;
an NMOS current mirror having a first input coupled to the PMOS current mirror, a second input coupled to a current source, and an output coupled to a second input of the comparator;
the comparator outputs a signal indicating current is flowing through the clamp element in the first direction.

13. The integrated circuit of claim 12 , wherein the clamp test circuit further includes:
a first flip-flop circuit having a data input coupled to the signal output by the comparator, an enable input coupled to an inverted ON/OFF signal and an output indicating proper operation through the clamp element.

14. The integrated circuit of claim 13 , wherein the clamp test circuit further includes:
a second flip-flop circuit having a data input coupled to the signal output by the comparator, an enable input coupled to a non-inverted ON/OFF signal and an output indicating proper operation through the blocking element.

15. A method of testing a clamp circuit for an insulated gate bipolar transistor (IGBT) comprising:
when applying voltage to a control gate of the IGBT, determining that current flows through a resistive element to a clamping device and not a blocking device, wherein the clamping device and the blocking device are coupled to the control gate;
when removing voltage from the control gate of the IGBT, determining that current

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Sicard Thierry

Classifications

• G01R19/16523

  using diodes, e.g. Zener diodes · CPC title

• G01R31/2608 Primary

  for testing bipolar transistors · CPC title

• H03K17/0828 Primary

  in composite switches · CPC title