System and method for monitoring voltage across isolation barrier

Patent metadata

Field	Value
Publication number	US-9608623-B1
Application number	US-201615198651-A
Country	US
Kind code	B1
Filing date	Jun 30, 2016
Priority date	Jun 30, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Systems and methods relating to voltage monitoring across isolation barriers are disclosed herein. In one example embodiment, an isolation system includes a low voltage circuit portion including a first control logic portion, and a high voltage circuit portion including a second control logic portion and an analog-to-digital converter portion. The system further includes a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage level and a second terminal coupled at least indirectly to a second connection having a second voltage level. The first control logic portion governs provision of an output signal generated based at least indirectly upon the second voltage level. Due to a galvanic barrier, the output signal can be provided for receipt by another device in a manner that avoids exposure of that device to an undesirably high current or power level.

First claim

What is claimed is:

1. An isolation system comprising:
a first low voltage (LV) circuit portion including a first control logic portion;
a first high voltage (HV) circuit portion including a second control logic portion and an analog-to-digital converter portion;
one or more coupling channels coupling the first LV and HV circuit portions by way of a galvanic barrier; and
a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage level and a second terminal coupled at least indirectly to a second connection having a second voltage level related to the first voltage level,
wherein the second terminal is coupled at least indirectly to a first port of the analog-to-digital converter portion,
wherein the first control logic portion governs provision of an output signal from an output terminal of the isolation system for receipt by another device, the output signal being generated based at least indirectly upon the second voltage level and being indicative of the first voltage level, and
wherein, due to the galvanic barrier, the output signal can be provided for receipt by the other device in a manner that avoids exposure of the other device to an undesirably high current or power level associated with the first HV circuit portion or the first transistor device.

2. The isolation system of claim 1 , wherein the LV and HV circuit portions, the one or more coupling channels, and the galvanic barrier are formed on an integrated circuit.

3. The isolation system of claim 2 , wherein the integrated circuit is an isolated gate driver integrated circuit.

4. The isolation system of claim 2 , wherein the transistor device is coupled to the integrated circuit by way of at least one resistor, and both the transistor device and the at least one resistor are components external to the integrated circuit.

5. The isolation system of claim 4 , wherein the at least one resistor includes a first resistor, wherein the second terminal is coupled to the first port by way of the first resistor, and wherein the first port is additionally coupled to the first connection by way of a second resistor, wherein the first and second resistors form a resistor divider circuit that is external of the integrated circuit.

6. The isolation system of claim 4 , wherein the one or more coupling channels include a pulse-width modulation (PWM) coupling channel, a data in coupling channel, a data out coupling channel, and an interrupt coupling channel.

7. The isolation system of claim 1 , wherein the output signal is a pulse-width modulation (PWM) signal, and wherein the first control logic portion is configured to determine one or both of a duty cycle or a frequency of the output signal.

8. The isolation system of claim 7 , further comprising a temperature sensing component positioned proximate the first transistor device and coupled at least indirectly to a second port of the analog-to-digital converter portion, wherein the temperature sensing component is configured to provide a signal to the second port that is indicative of a temperature of at least a portion of the first transistor device or a region proximate to the first transistor device.

9. The isolation system of claim 8 , wherein the first control logic portion is configured to adjust one or both of the duty cycle or the frequency of the output signal to allow for multiplexed communication of the output signal so that the output signal is, at least at different times, indicative of each of the first voltage level and the temperature.

10. The isolation system of claim 9 , wherein the first control logic portion is configured so that the output signal includes a first component having a first frequency that is indicative of the voltage level and a second component having a second frequency that is indicative of the temperature.

11. The isolation system of claim 1 , wherein one or both of the second control logic portion and the analog-to-digital converter portion is or are configured to cause one or both of processing or conversion of an input value or input signal received at the first port to be deferred until after a first time delay has elapsed since an occurrence of a change in a pulse-width modulation (PWM) control signal received at the first control logic portion or provided by the first control logic portion for receipt by the second control logic portion.

12. The isolation system of claim 11 , wherein the second control logic portion is further configured to defer sending a data out signal based upon the processing or conversion of the input value or input signal until the second control logic portion receives a request analog-to-digital conversion signal from the first control logic portion.

13. The isolation system of claim 1 , wherein the first transistor device is an insulated-gate bipolar transistor (IGBT).

14. The isolation system of claim 1 , further comprising:
a second LV circuit portion including an additional first control logic portion;
a second HV circuit portion including an additional second control logic portion and an additional analog-to-digital converter portion;
one or more coupling channels coupling the second LV and HV circuit portions by way of a galvanic barrier; and
a second transistor device having an additional first terminal coupled at least indirectly to a third connection having a third voltage level and an additional second terminal coupled at least indirectly to the second connection,
wherein the additional second terminal is coupled at least indirectly to an additional first port of the additional analog-to-digital converter portion.

15. A control system comprising the isolation system of claim 1 , wherein the control system additionally includes a microprocessor coupled at least indirectly to the LV circuit portion of the isolation system, the microprocessor being the other device, wherein the microprocessor is configured to provide one or more input signals for receipt at the LV circuit portion and to receive the output signal.

16. A system comprising the isolation system of claim 1 and additionally including a controlled device that is coupled at least indirectly to two or more of the first, second, and third connections, wherein the controlled device is either a motor controller or an inverter.

17. A method of monitoring a voltage level in an isolated manner, the method comprising:
receiving a first pulse-width modulation (PWM) signal that transitions between low and high levels at a first time;
upon an expiration of a first time delay subsequent to the first time, performing an analog-to-digital conversion of a first input signal or first input value that is received, at least indirectly from a first terminal of a first transistor device, by a first input port of an analog-to-digital converter portion of a high voltage (HV) circuit portion of an isolation system so as to generate a result signal;
upon receiving a request signal from a low voltage (LV) circuit portion of the isolation system at the HV circuit portion, sending the result signal or a further signal based upon the result signal across a galvanic barrier by way of a coupling channel to the LV circuit portion;
determining one or both of a duty cycle and a frequency of a second PWM signal to be output from the LV circuit portion for receipt by another device, wherein the second PWM signal is based upon the result signal and indicative of the first input signal or first input value; and
sending the second PWM signal for receipt by the other device,
wherein, due to the galvanic barrier, the

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Kandah Ibrahim
• Gauen Kim
• Krohn Neil

Classifications

• G01R19/0084

  Measuring voltage only · CPC title

• H02P31/00

  Arrangements for regulating or controlling electric motors not provided for in groups H02P1/00 - H02P5/00, H02P7/00 or H02P21/00 - H02P29/00 · CPC title

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• G01R15/144

  Measuring arrangements for voltage not covered by other subgroups of G01R15/14 · CPC title

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title