Methods for reducing contact depth variation in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-12438049-B2
Application number	US-202217818289-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	Aug 30, 2017
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an isolation feature disposed over the substrate;
a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature;
a gate structure disposed directly over the isolation feature;
a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure;
a first etch stop layer disposed between the first dielectric layer and the isolation feature;
a second dielectric layer disposed directly above the first dielectric layer;
a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer, wherein the first etch stop layer is also disposed between the gate structure and the second etch stop layer; and
a first conductive feature directly above the isolation feature and penetrating through the second dielectric layer and the second etch stop layer to directly contact a top surface of the first dielectric layer.

2. The integrated circuit of claim 1 , wherein a top surface of the first dielectric layer is at a same level as a top surface of the fin or below the top surface of the fin by less than or equal to 15 nanometers.

3. The integrated circuit of claim 1 , wherein the first etch stop layer is also disposed between the first dielectric layer and the gate structure.

4. The integrated circuit of claim 1 , further comprising a second gate structure disposed directly above the fin, wherein the second dielectric layer is also disposed directly above the fin.

5. The integrated circuit of claim 4 , wherein the first etch stop layer is also disposed between the fin and the second dielectric layer and between the second gate structure and the second dielectric layer.

6. The integrated circuit of claim 4 , wherein a topmost surface of the first etch stop layer is at a same level as a topmost surface of the second etch stop layer.

7. The integrated circuit of claim 6 , further comprising a third etch stop layer in direct contact with the topmost surfaces of the first and the second etch stop layers.

8. The integrated circuit of claim 4 , further comprising a second conductive feature directly above the fin and directly contacting a source/drain feature of the fin.

9. The integrated circuit of claim 8 , wherein the first conductive feature penetrates through the second etch stop layer and the second conductive feature penetrates through the first and the second etch stop layers.

10. The integrated circuit of claim 8 , wherein each of the first and the second conductive features are disposed between portions of the first etch stop layer and between portions of the second etch stop layer.

11. The integrated circuit of claim 8 , further comprising a third dielectric layer over the second dielectric layer, wherein the first and the second conductive features penetrate through the second and the third dielectric layers.

12. An integrated circuit comprising:
a substrate;
an isolation feature disposed over the substrate;
a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature;
a gate structure disposed directly over the isolation feature;
a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, wherein a topmost surface of the first dielectric layer is at a same level as a topmost flat surface of the fin or below the topmost flat surface of the fin by less than or equal to 15 nanometers;
a first etch stop layer disposed between the first dielectric layer and the isolation feature and between the first dielectric layer and the gate structure;
a second dielectric layer disposed directly above the first dielectric layer;
a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer, wherein the first etch stop layer is also disposed between the gate structure and the second etch stop layer; and
a conductive feature directly above the isolation feature and directly contacting the first dielectric layer.

13. The integrated circuit of claim 12 , further comprising:
a third etch stop layer over the second dielectric layer; and
a third dielectric layer over the third etch stop layer,
wherein the conductive feature penetrates through the third dielectric layer, the third etch stop layer, and the second dielectric layer.

14. The integrated circuit of claim 13 , wherein the third etch stop layer is in direct contact with top surfaces of the first and the second etch stop layers.

15. The integrated circuit of claim 13 , further comprising:
a second gate structure disposed directly above the fin,
wherein the second dielectric layer is also disposed directly above the fin,
wherein the first etch stop layer is also disposed between the fin and the second dielectric layer and between the second gate structure and the second dielectric layer.

16. The integrated circuit of claim 15 , further comprising a second conductive feature directly above the fin and directly contacting a source/drain feature of the fin.

17. An integrated circuit comprising:
a substrate;
an isolation feature disposed over the substrate;
a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature;
a first gate structure disposed directly over the fin;
a second gate structure disposed directly over the isolation feature;
a first dielectric layer disposed directly above the isolation feature and adjacent to the second gate structure;
a first etch stop layer disposed between the first dielectric layer and the isolation feature and between the first dielectric layer and the second gate structure;
a second dielectric layer disposed directly above the first dielectric layer and directly above the fin;
a second etch stop layer disposed between the first and the second dielectric layers, between the first gate structure and the second dielectric layer, and between the second gate structure and the second dielectric layer, wherein the first etch stop layer is also disposed between the second gate structure and the second etch stop layer;
a first conductive feature directly above the fin and penetrating through the second dielectric layer and the second etch stop layer; and
a second conductive feature directly above the isolation feature and directly contacting the first dielectric layer.

18. The integrated circuit of claim 17 , wherein the first etch stop layer is also disposed between the fin and the second etch stop layer and the first conductive feature penetrates through the first etch stop layer.

19. The integrated circuit of claim 17 , further comprising:
a third etch stop layer over the second dielectric layer; and
a third dielectric layer over the third etch stop layer,
wherein the first and the second conductive features penetrate through the third dielectric layer and the third etch stop layer.

20. The integrated circuit of claim 19 , wherein the third etch stop layer is in direct contact with top surfaces of the second dielectric layer, the first etch stop layer, and the second etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yun
• Lee Chen-Ming
• Yang Fu-Kai
• Huang Yi-Jyun
• Wang Sheng-Hsiung
• Wang Mei-Yun

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title