Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016336429-A1
Application number	US-201514714227-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

First claim

1 . A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer; forming a source/drain structure in the fin structure; forming a gate structure over a part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction; forming an interlayer dielectric layer over the fin structure, the source/drain structure and the gate structure; forming a contact hole in the interlayer dielectric layer so as to expose the source/drain structure; forming a cap layer including silicon phosphide in the contact hole; and forming a contact metal layer over the cap layer.

2 . The method of claim 1 , further comprising forming an alloy layer between the cap layer and the contact metal layer.

3 . The method of claim 1 , further comprising:
between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

4 . The method of claim 1 , wherein:
the fin structure is made of germanium or germanium compound.

5 . (canceled)

6 . The method of claim 3 , wherein:
the fin structure is made of germanium or germanium compound, and the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

7 . (canceled)

8 . The method of claim 1 , wherein the source/drain structure includes germanium phosphide.

9 - 20 . (canceled)

21 . A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer; forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction; recessing the fin structure not covered by the dummy gate structure; forming a source/drain structure in the recessed fin structure; forming an insulating layer over the dummy gate structure and the source/drain structure; removing the dummy gate structure, thereby forming a gate space; forming a metal gate structure in the gate space; forming a contact hole in the insulating layer so as to expose the source/drain structure; forming a cap layer including silicon phosphide in the contact hole; and forming a contact metal layer over the cap layer.

22 . The method of claim 21 , further comprising forming an alloy layer between the cap layer and the contact metal layer.

23 . The method of claim 21 , further comprising:
between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

24 . The method of claim 21 , wherein:
the fin structure is made of germanium or germanium compound.

25 . (canceled)

26 . The method of claim 23 , wherein:
the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

27 . (canceled)

28 . The method of claim 21 , wherein the source/drain structure includes germanium phosphide.

29 . A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming plural fin structures over a substrate, the fin structures extending in a first direction, each of the fin structures including an upper layer, a part of the upper layer being exposed from an isolation insulating layer; forming source/drain structures in the fin structures, respectively; forming one or more gate structures over a part of the fin structures, the one or more gate structures extending in a second direction perpendicular to the first direction; forming an interlayer dielectric layer over the fin structures and the source/drain structures; forming a contact hole in the interlayer dielectric layer so as to expose the source/drain structures; forming a cap layer including silicon phosphide in the contact hole; and forming a contact metal layer over the cap layer.

30 . The method of claim 29 , further comprising forming an alloy layer between the cap layer and the contact metal layer.

31 . The method of claim 29 , further comprising:
between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

32 . The method of claim 31 , wherein:
the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Cheng-Yi
• Yeh Chih Chieh
• Chang Chih-Sheng
• Chiang Hung-Li
• Chen Hung-Ming
• Yeo Yee-Chia

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title