Method for semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-9299803-B2
Application number	US-201414332581-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	Jul 16, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Provided is a method of forming a semiconductor device. The method includes providing a substrate having n-type doped source/drain features; depositing a flowable dielectric material layer over the substrate; and performing a wet annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius (° C.) and a second portion performed at temperatures above 850° C. wherein the second portion is performed for a shorter duration than the first portion. In embodiments, the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900° C. to about 1,050° C. and a spike duration ranging from about 0.7 seconds to about 10 seconds. The wet annealing process satisfies thermal budget for converting the flowable dielectric material layer to a dense oxide layer while maintaining tensile strain in an n-channel between the doped source/drain features.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
providing a substrate, the substrate having n-type doped source/drain features;
depositing a flowable dielectric material layer over the substrate;
performing a wet annealing process to the flowable dielectric material layer; and
performing a dry annealing process to the flowable dielectric material layer, wherein:
the wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius and a second portion performed at temperatures above 850 degrees Celsius;
the second portion is performed for a shorter duration than the first portion;
the dry annealing process includes a third portion performed at a temperature below 600 degrees Celsius and a fourth portion performed at temperatures above 850 degrees Celsius; and
the fourth portion is performed for a shorter duration than the third portion.

2. The method of claim 1 , wherein the first portion is performed at a temperature ranging from about 500 degrees Celsius to about 550 degrees Celsius for a duration ranging from about 100 seconds to about 1,800 seconds.

3. The method of claim 1 , wherein the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius and a spike duration ranging from about 0.7 seconds to about 10 seconds as measured at a temperature 50 degrees Celsius below the peak temperature.

4. The method of claim 3 , wherein the spike temperature ramp profile has a temperature ramp-up rate at least 50 degrees Celsius per second and a temperature ramp-down rate at least 50 degrees Celsius per second.

5. The method of claim 3 , wherein the spike temperature ramp profile has a temperature ramp-up rate ranging from about 50 degrees Celsius per second to about 250 degrees Celsius per second and a temperature ramp-down rate ranging from about 50 degrees Celsius per second to about 200 degrees Celsius per second.

6. The method of claim 1 , wherein the wet annealing process is performed in an environment containing H 2 O 2 or H 2 O.

7. The method of claim 1 , wherein:
the third portion is performed at a temperature ranging from about 500 degrees Celsius to about 550 degrees Celsius for a duration ranging from about 10 seconds to about 1,800 seconds; and
the fourth portion has a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius and a spike duration ranging from about 0.7 seconds to about 10 seconds as measured at a temperature 50 degrees Celsius below the peak temperature.

8. A method of forming a semiconductor device, the method comprising:
providing a substrate having a gate structure;
forming n-type doped source/drain features adjacent to the gate structure;
depositing a flowable dielectric material layer over the substrate;
performing a wet annealing process to the flowable dielectric material layer, wherein the wet annealing process includes a first portion performed below 600 degrees Celsius and a second portion having a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius; and
performing a dry annealing process to the flowable dielectric material layer, wherein the dry annealing process includes a third portion performed below 600 degrees Celsius and a fourth portion having a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius.

9. The method of claim 8 , wherein the spike temperature ramp profile of the second portion has a spike duration ranging from about 0.7 seconds to about 10 seconds as measured at a temperature 50 degrees Celsius below the peak temperature.

10. The method of claim 8 , wherein forming the n-type doped source/drain features includes:
etching recesses adjacent to the gate structure; and
epitaxially growing silicon in the recesses having a phosphorus dopant concentration ranging from about 1×e 21 cm −3 to about 4×e 21 cm −3 .

11. The method of claim 8 , wherein forming the n-type doped source/drain features includes:
etching recesses adjacent to the gate structure; and
epitaxially growing silicon in the recesses having an equivalent carbon dopant concentration ranging from about 1% to about 2.5% and a phosphorus dopant concentration ranging from about 1×e 20 cm −3 to about 7×e 20 cm −3 .

12. The method of claim 8 , wherein forming the n-type doped source/drain features includes:
etching recesses adjacent to the gate structure;
epitaxially growing a first layer of silicon in the recesses having an equivalent carbon dopant concentration ranging from about 1% to about 2.5% and a phosphorus dopant concentration ranging from about 1×e 20 cm −3 to about 7×e 20 cm −3 ; and
epitaxially growing a second layer of silicon over the first layer of silicon, wherein the second layer of silicon has a phosphorus concentration ranging from about 1×e 21 cm −3 to about 3×e 21 cm −3 .

13. The method of claim 12 , wherein the first layer of silicon is formed to have a thickness ranging from about 4.5 nm to about 7.5 nm and the second layer of silicon is formed to have a thickness ranging from about 22.5 nm to about 45.5 nm.

14. The method of claim 8 , wherein the spike temperature ramp profile of the fourth portion has a spike duration ranging from about 0.7 seconds to about 10 seconds as measured at a temperature 50 degrees Celsius below the peak temperature.

15. A method of forming a semiconductor device, the method comprising:
providing a substrate, the substrate having a gate structure and n-type doped source/drain features adjacent to the gate structure;
forming a contact etch stop (CES) layer over the gate structure and the n-type doped source/drain features;
forming an inter-layer dielectric (ILD) layer over the substrate by depositing a flowable dielectric material;
performing a first wet annealing process to the ILD layer, wherein the first wet annealing process includes a first portion performed below 600 degrees Celsius and a second portion having a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius; and
performing a first dry annealing process to the ILD layer, wherein the first dry annealing process includes a third portion performed below 600 degrees Celsius and a fourth portion having a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius.

16. The method of claim 15 , further comprising:
performing a chemical mechanical planarization (CMP) process to the ILD layer until a top surface of the CES layer is exposed; and
performing a second wet annealing process to the ILD layer, wherein the second wet annealing process includes a fifth portion performed below 600 degrees Celsius and a sixth portion having a spike temperature ramp profile with a peak temperature ranging from about 900 degrees Celsius to about 1,050 degrees Celsius.

17. The method of claim 16 , wherein at least one of the second and the sixth portions has a spike duration ranging from about 0.7 seconds to about 10 seconds as measured at a temperature 50 degrees Celsius below the respective peak temperature.

18. The method of claim 16 , further comprising:
performing a second dry annealing process to the ILD layer after the second wet annealing process, wherein the second dry annealing process includes a seventh por

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsai Chung Hsiung
• Lu Wei-Yuan

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/642

  Chemical etching · CPC title