Semiconductor device including two-dimensional semiconductor material

Patent metadata

Field	Value
Publication number	US-12408399-B2
Application number	US-202418761779-A
Country	US
Kind code	B2
Filing date	Jul 2, 2024
Priority date	Jan 21, 2020
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of gate electrodes on the substrate, each of the plurality of gate electrodes having a shape with a height greater than a width;
a connection electrode on the substrate, the connection electrode connecting the plurality of gate electrodes to each other;
a plurality of gate dielectrics on the plurality of gate electrodes;
a plurality of channel layers on the plurality of gate dielectrics, the plurality of channel layers comprising a two-dimensional semiconductor material; and
a source electrode and a drain electrode that are electrically connected to the plurality of channel layers.

2. The semiconductor device of claim 1 , wherein the plurality of gate electrodes are arranged side by side with each other.

3. The semiconductor device of claim 1 , wherein the connection electrode is provided in one piece with the plurality of gate electrodes.

4. The semiconductor device of claim 1 , further comprising:
an interconnect electrically connected to the connection electrode.

5. The semiconductor device of claim 4 , wherein the interconnect contacts the connection electrode between the plurality of channel layers.

6. The semiconductor device of claim 5 , wherein
the plurality of gate dielectrics include a first gate dielectric and a second gate dielectric, and
a portion of an upper surface of the connection electrode is opened through the first gate dielectric and the second gate dielectric to provide an opened portion of the upper surface of the connection electrode.

7. The semiconductor device of claim 6 , wherein the interconnect contacts the opened portion of the upper surface of the connection electrode.

8. The semiconductor device of claim 7 , wherein the interconnect is positioned between the source electrode and the drain electrode.

9. The semiconductor device of claim 5 , wherein a portion of a lower surface of the connection electrode is opened through the substrate to provide an opened portion of the lower surface of the connection electrode.

10. The semiconductor device of claim 9 , wherein the interconnect contacts the opened portion of the lower surface of the connection electrode.

11. The semiconductor device of claim 1 , wherein the two-dimensional semiconductor material comprises graphene, black phosphorus, a transition metal dichalcogenide (TMD), or a combination thereof.

12. The semiconductor device of claim 1 , wherein the two-dimensional semiconductor material has a monolayer structure or a multilayer structure.

13. The semiconductor device of claim 1 , wherein each of the plurality of channel layers has a thickness of greater than 0 nm and about 10 nm or less.

14. The semiconductor device of claim 1 , wherein the substrate comprises an insulating material.

15. The semiconductor device of claim 14 , wherein the substrate further comprises a semiconductor material.

16. The semiconductor device of claim 1 , wherein each of the plurality of gate electrodes has a height/width ratio that is greater than about 1 but less than about 20.

17. The semiconductor device of claim 1 , wherein each of the plurality of gate electrodes comprises a metallic material or a conductive oxide.

18. The semiconductor device of claim 1 , wherein each of the plurality of gate dielectrics comprises a high-k material, a ferroelectric material, or both the high-k material and the ferroelectric material.

19. The semiconductor device of claim 1 , wherein each of the plurality of gate dielectrics comprises a charge trapping material.

20. The semiconductor device of claim 1 , wherein the source electrode and the drain electrode overlap the plurality of gate electrodes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minhyun
• Seol Minsu
• Cho Yeonchoo
• Shin Hyeonjin

Classifications

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title