Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10056498-B2
Application number	US-201715401463-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Nov 29, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
depositing a two-dimensional (2D) material over a substrate to form a channel structure;
forming a passivation structure with a first thickness over the channel structure;
forming isolation structures to define a plurality of device regions;
by using an atomic layer etch process, removing a desired number of layers from the passivation structure in each of the plurality of device regions to form a plurality of thinned passivation structures;
forming a gate stack over each of the plurality of thinned passivation structures; and
forming source and drain contacts in the plurality of device regions, the source and drain contacts having side contacts with the channel structure.

2. The method of claim 1 , further comprising removing damaged layers of the passivation structure prior to the atomic layer etch process and after formation of the isolation structures.

3. The method of claim 1 , wherein the 2D material comprises a semiconducting 2D material including black phosphorous and the passivation structure comprises a 2D insulator material including boron nitride.

4. The method of claim 3 , further comprising forming the channel structure and the passivation structure using an atomic layer deposition (ALD) process, and wherein the first thickness is within a range of about 100-200 layers.

5. The method of claim 1 , wherein the 2D material comprises a semiconducting 2D material including molybdenum disulfide (MoS 2 ) and the passivation structure comprises a 2D insulator material including alumina (Al 2 O 3 ).

6. The method of claim 1 , further comprising removing portions of the isolation structures and the plurality of thinned passivation structures to allow the source and drain contacts to have side contacts with the channel structure and the plurality of thinned passivation structures.

7. The method of claim 1 , wherein the 2D material comprises a 2D semiconductor, and wherein the 2D semiconductor comprises a transition metal dichalcogenide (TMD) including molybdenum disulfide (MoS 2 ), black phosphorous, or graphene.

8. The method of claim 1 , wherein forming the gate stack comprises forming a high-k oxide over a respective thinned passivation structures of the plurality of thinned passivation structures.

9. The method of claim 1 , wherein the substrate comprises one of silicon (Si), silicon dioxide (SiO 2 ), silicon covered with a dialectic material, or germanium (Ge).

10. The method of claim 1 , wherein each of the plurality of thinned passivation structures has a different thickness within a range of about 1-100 layers of a 2D insulator material.

11. A method for manufacturing a semiconductor device, comprising:
forming a channel structure over a substrate;
forming an interfacial structure over the channel structure;
forming isolation regions penetrating the substrate to define device regions;
removing damaged layers of the interfacial structure;
by using an atomic layer etch process, removing a desired number of layers from the interfacial structure in each of the device regions to form isolated thinned interfacial structures;
forming a gate stack over each of the isolated thinned interfacial structures; and
forming source and drain contacts in the device regions by removing portions of the isolation regions and the isolated thinned interfacial structures to allow source and drain contacts having side contacts with the channel structure and isolated thinned interfacial structures.

12. The method of claim 11 , further comprising removing damaged layers of the interfacial structure after formation of the isolation regions.

13. The method of claim 11 , wherein the channel structure comprises a two-dimensional (2D) material, wherein the 2D material comprises a semiconducting 2D material including black phosphorous, and the interfacial structure comprises a 2D insulator material including boron nitride.

14. The method of claim 13 , further comprising forming the channel structure and the interfacial structure using an atomic layer deposition (ALD) process.

15. The method of claim 11 , wherein the 2D material comprises a 2D semiconductor, and wherein the 2D semiconductor comprises a transition metal dichalcogenide (TMD) including molybdenum disulfide (MoS 2 ), black phosphorous, and graphene.

16. The method of claim 11 , wherein the interfacial structure comprises a 2D insulator material including alumina (Al 2 O 3 ) or hexagonal boron nitride.

17. The method of claim 11 , wherein forming the gate stack comprises forming a high-k oxide over a respective isolated thinned interfacial structure.

18. A method for manufacturing a semiconductor device, comprising:
depositing a two-dimensional (2D) material over a substrate to form a channel structure;
forming a passivation structure with a first thickness over the channel structure;
forming isolation structures in the substrate to define a plurality of device regions;
by using an atomic layer etch process, removing a desired number of layers from the passivation structure in each of the plurality of device regions to form a plurality of thinned passivation structures;
forming a gate stack over each of the plurality of thinned passivation structures;
forming source and drain contacts in the plurality of device regions, the source and drain contacts having side contacts with the channel structure;
forming a metal layer over the gate stack and the source and drain contacts.

19. The method of claim 18 , further comprising removing damaged layers of the passivation structure prior to the atomic layer etch process and after formation of the isolation structures.

20. The method of claim 18 , wherein the 2D material comprises a semiconducting 2D material including black phosphorous and the passivation structure comprises a 2D insulator material including boron nitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Ling-Yen
• Chang Chih-Sheng
• Tsai Wilman
• Lin Yu-Ming

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6506

  Formation of intermediate materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title