Transistors and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9257508-B2
Application number	US-201213595580-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Jan 26, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer.

First claim

What is claimed is:

1. A transistor, comprising:
a gate on a substrate;
a channel layer having a three-dimensional (3D) channel region partially covering both side surfaces and a top surface of the gate;
a source electrode contacting a first region of the channel layer,
wherein the source electrode includes,
a first source electrode portion, an upper surface of the first source electrode portion being higher than an upper surface of the 3D channel region,
a second source electrode portion between the first source electrode portion and the 3D channel region,
bottom surfaces of the first and second source electrode portions directly contact an upper surface of the channel layer, and
a thickness of the first source electrode portion being greater than a thickness of the second source electrode portion; and

a drain electrode contacting a second region of the channel layer.

2. The transistor of claim 1 , wherein the channel layer is on the substrate.

3. The transistor of claim 1 , wherein the channel layer includes graphene.

4. The transistor of claim 1 , wherein the source electrode and the drain electrode are respectively at sides of the gate.

5. The transistor of claim 4 , wherein the first source electrode portion is spaced apart from a first side of the 3D channel region, and
the drain electrode includes a first drain electrode portion spaced apart from a second side of the 3D channel region.

6. The transistor of claim 5 , wherein an upper surface of the first drain electrode portion is higher than the upper surface of the 3D channel region.

7. The transistor of claim 5 , wherein
the drain electrode further includes a second drain electrode portion between the first drain electrode portion and the 3D channel region.

8. The transistor of claim 7 , wherein the upper surface of second source electrode portion and an upper surface of the second drain electrode portion are even with, or lower, than the upper surface of the 3D channel region.

9. The transistor of claim 7 , wherein an effective channel length of the transistor is adjusted according to a height of each of the second source electrode portion and the second drain electrode portion.

10. The transistor of claim 1 , wherein,
the source electrode includes,
the first source electrode portion on the channel layer at one side of the gate, and
the second source electrode portion connected to the first source electrode portion, the second source electrode portion being on a first side wall of the gate, and

the drain electrode includes,
a first drain electrode portion on the channel layer at another side of the gate, and
a second drain electrode portion connected to the first drain electrode portion, the second drain electrode portion being on a second side wall of the gate.

11. The transistor of claim 1 , wherein the gate includes a first gate and a second gate spaced apart from each other in a horizontal direction,
the source electrode includes a first source electrode and a second source electrode spaced apart from each other with the first and second gates therebetween, and
the drain electrode is between the first and second gates.

12. The transistor of claim 11 , wherein the first source electrode includes a first primary source electrode portion at one side of the first and second gates,
the second source electrode includes a second primary source electrode portion at another side of the first and second gates, and
the first and second primary source electrode portions collectively forming the first source electrode portion.

13. The transistor of claim 12 , wherein the first source electrode further includes a first secondary source electrode portion between the first primary source electrode portion and the first gate, and
the second source electrode further includes a second secondary source electrode portion between the second primary source electrode portion and the second gate.

14. The transistor of claim 13 , wherein the first secondary source electrode portion and the second secondary source electrode portion each have a height less than a height of each of the first primary source electrode portion and the second primary source electrode portion.

15. The transistor of claim 13 , wherein the drain electrode has a height equal to a height of each of the first secondary source electrode portion and the second secondary source electrode portion.

16. The transistor of claim 1 , further comprising:
an insulating layer on the substrate, the gate being on the insulating layer,
wherein the channel layer is on the insulating layer so as to cover at least a portion of the gate.

17. The transistor of claim 1 , wherein the substrate is one selected from a polymer substrate, a glass substrate and a silicon substrate.

18. A method of manufacturing a transistor, the method comprising:
forming a stacked structure including a gate and a channel layer having a three-dimensional (3D) channel region partially covering both side surfaces and a top surface of the gate;
forming a source electrode contacting a first region of the channel layer,
wherein the forming a source electrode includes,
forming a first source electrode portion, an upper surface of the first source electrode portion being higher than an upper surface of the 3D channel region,
forming a second source electrode portion between the first source electrode portion and the 3D channel region,
bottom surfaces of the first and second source electrode portions directly contacting an upper surface of the channel layer, and
a thickness of the first source electrode portion being greater than a thickness of the second source electrode portion; and

forming a drain electrode contacting a second region of the channel layer.

19. The method of claim 18 , wherein the channel layer includes graphene.

20. The method of claim 18 , wherein the forming of the stacked structure includes,
forming a mold layer on a first substrate, the mold layer including a trench;
forming the channel layer on the mold layer, the channel layer having a 3D structure due to the trench;
forming a gate insulating layer on the channel layer; and
forming a gate in the trench.

21. The method of claim 20 , wherein the forming of the stacked structure further includes,
attaching a second substrate to the gate and the gate insulating layer; and
removing the first substrate.

22. The method of claim 21 , wherein the forming of the stacked structure includes forming a plurality of device regions,
the forming of the mold layer includes forming a plurality of trenches respectively corresponding to the plurality of device regions, and
the gate is formed in each of the plurality of trenches.

23. The method of claim 22 , further comprising:
separating the plurality of device regions by patterning the stacked structure.

24. The method of claim 23 , further comprising:
forming a sacrificial layer between the first substrate and the stacked structure,
wherein the removing of the first substrate includes etching the sacrificial layer by injecting an etchant between the plurality of device regions.

25. The method of claim 20 , wherein the channel layer includes graphene.

26. The method of claim 25 , wherein the mold layer is a catalyst layer, and
the graphene is formed from the catalyst layer.

27. The method of claim 20 , wherein at least a portion of

Assignees

• Lee Chang-Seung
• Lee Joo-Ho
• Kim Yong-Sung
• Kim Jun-Seong
• Moon Chang-Youl
• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Seung
• Lee Joo-Ho
• Kim Yong-Sung
• Kim Jun-Seong
• Moon Chang-Youl

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title