Thin film transistor, manufacturing method of the same, and display device with the thin film transistor

Patent metadata

Field	Value
Publication number	US-2016365459-A1
Application number	US-201615010169-A
Country	US
Kind code	A1
Filing date	Jan 29, 2016
Priority date	Jun 9, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

A thin film transistor includes an insulating pattern disposed on a substrate, a gate electrode disposed on the insulating pattern, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, and a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the semiconductor layer and distanced apart from each other. The gate electrode surrounds an upper surface and a side surface of the insulating pattern and overlaps a first portion of a substrate surface.

First claim

What is claimed is:

1 . A thin film transistor, comprising:
an insulating pattern disposed on a substrate; a gate electrode disposed on the insulating pattern; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; and a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the semiconductor layer and distanced apart from each other, wherein the gate electrode surrounds an upper surface and a side surface of the insulating pattern and overlaps a first portion of a substrate surface.

2 . The thin film transistor of claim 1 , wherein the gate electrode comprises:
a first portion contacting the first portion of the substrate surface along a first direction; and a second portion contacting the side surface of the insulating pattern and extending from the first portion of the gate electrode to a third portion of the gate electrode along a second direction that substantially perpendicular to the first direction, the third portion of the gate electrode contacting the upper surface of the insulating pattern and extending from the second portion of the gate electrode to another part of the second portion of the gate electrode.

3 . The thin film transistor of claim 1 , wherein the insulating pattern comprises at least one of silicon nitride (SiN X ), carbon-injected silicon oxide (SiOC), and an organic polymer.

4 . The thin film transistor of claim 1 , further comprising a filling layer covering a side surface of the gate electrode between the gate electrode and the gate insulating layer.

5 . The thin film transistor of claim 4 , wherein the filling layer comprises at least one of a transparent insulating material and a color filter layer.

6 . The thin film transistor of claim 1 , wherein the insulating pattern comprises an opening portion exposing a second portion of the substrate surface.

7 . The thin film transistor of claim 6 , wherein the gate electrode is disposed in the opening portion.

8 . A method of manufacturing a thin film transistor, comprising:
forming an insulating pattern on a substrate; forming a gate electrode on the insulating pattern; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer; and forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being distanced apart from each other on the semiconductor layer, wherein the gate electrode surrounds an upper surface and a side surface of the insulating pattern and overlaps a first portion of a substrate surface.

9 . The method of claim 8 , wherein the forming of the gate electrode comprises:
forming a conductive layer on the insulating pattern and the substrate; forming a photoresist pattern on the conductive layer; forming the gate electrode by etching the conductive layer; and removing the photoresist pattern.

10 . The method of claim 9 , wherein the etching of the conductive layer comprises an anisotropic etching method.

11 . The method of claim 8 , wherein the insulating pattern comprises at least one of silicon nitride (SiN X ), carbon-injected silicon oxide (SiOC), and an organic polymer.

12 . The method of claim 8 , further comprising forming a filling layer between the gate electrode and the gate insulating layer and covering a side surface of the gate electrode.

13 . The method of claim 12 , wherein the filling layer comprises at least one of a transparent insulating material and a color filter.

14 . The method of claim 8 , wherein the insulating pattern comprises an opening portion exposing a second portion of the substrate surface.

15 . A display device, comprising:
a display element; and a thin film transistor configured to provide a driving signal to the display element, wherein the thin film transistor comprises:
an insulating pattern disposed on a substrate;
a gate electrode disposed on the insulating pattern;
a gate insulating layer disposed on the gate electrode;
a semiconductor layer disposed on the gate insulating layer; and
a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode and the drain electrode being disposed to be distanced apart from each other,
wherein the gate electrode surrounds an upper surface and a side surface of the insulating pattern and overlaps a portion of a substrate surface.

16 . The display device of claim 15 , wherein the display device comprises:
a first electrode coupled to the thin film transistor; a second electrode configured to form an electric field along with the first electrode; and a liquid crystal layer configured to be driven by the electric field.

17 . The display device of claim 15 , wherein the display device comprises:
a first electrode coupled to the thin film transistor; an organic light emitting layer disposed on the first electrode; and a second electrode disposed on the organic light emitting layer and configured to drive the organic light emitting layer along with the first electrode.

Assignees

• Samsung Display Co Ltd

Inventors

• Hong Sung Jin
• Kang Jae Woong
• Kang Jong Hyuk
• Kim Dae Hyun
• Park Jae Byung
• Lee Joo Yeol
• Im Hyun Deok
• Cho Hyun Min
• Roh Nam Seok

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title