Thin-sheet FinFET device

Patent metadata

Field	Value
Publication number	US-9711647-B2
Application number	US-201414304695-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jun 13, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a top surface defined thereupon;
a feature disposed on the substrate and extending above the top surface;
a material layer that includes a transition metal dichalcogenide disposed on the feature, wherein a channel region, a source region, and a drain region are defined in the material layer, the channel region being disposed between the source region and the drain region; and
a gate stack disposed on the channel region of the material layer.

2. The semiconductor device of claim 1 , wherein the material layer includes at least one monolayer of the transition metal dichalcogenide.

3. The semiconductor device of claim 1 , wherein the material layer includes a portion disposed on the top surface of the substrate, and wherein the portion is not disposed on the feature.

4. The semiconductor device of claim 1 , wherein the feature includes a plurality of side surfaces and wherein the material layer is disposed on each surface of the plurality of side surfaces.

5. The semiconductor device of claim 4 , wherein the feature further includes a topmost surface, and wherein the material layer is further disposed on the topmost surface of the feature.

6. The semiconductor device of claim 1 , wherein the feature includes a topmost surface free of the material layer.

7. The semiconductor device of claim 6 , wherein the material layer includes a first channel region disposed on a first side surface of the feature and a second channel region disposed on a second side surface of the feature.

8. The semiconductor device of claim 7 , wherein the first channel region forms a first transistor, and wherein the second channel region forms a second transistor different from the first transistor.

9. The semiconductor device of claim 1 , wherein the feature includes a dielectric material.

10. A circuit device comprising:
a fin formed on a substrate and having a transistor formed thereupon, wherein the fin includes:
a rib structure; and
a transition metal dichalcogenide sheet material formed on at least one surface of the rib structure, wherein the transition metal dichalcogenide sheet material has a channel region of the transistor defined thereupon; and

a gate formed over the channel region of the transition metal dichalcogenide sheet material.

11. The circuit device of claim 10 , wherein the rib structure includes a dielectric material.

12. The circuit device of claim 10 , wherein the transition metal dichalcogenide material includes a transition metal and a chalcogenide, wherein the transition metal is selected from the group consisting of Zr, Ta, Nb, W, Mo, Ga, and Sn, and further wherein the chalcogenide is selected from the group consisting of Se, S, and Te.

13. The circuit device of claim 10 , wherein the transition metal dichalcogenide sheet material includes a portion formed on an isolation feature of the substrate, and wherein the portion extends away from the rib structure.

14. The circuit device of claim 10 , wherein the rib structure includes a top surface and opposing side surfaces, and wherein the transition metal dichalcogenide sheet material is formed on at least the opposing side surfaces of the rib structure.

15. The circuit device of claim 14 , wherein the transition metal dichalcogenide sheet material is further formed on the top surface of the rib structure.

16. The circuit device of claim 14 , wherein the top surface is free of the transition metal dichalcogenide sheet material.

17. A semiconductor device, comprising:
a fin feature extending from a substrate;
a transition metal dichalcogenide layer wrapping the fin feature;
a gate stack wrapping a portion of the transition metal dichalcogenide layer, such that a channel region is defined in the transition metal dichalcogenide layer.

18. The semiconductor device of claim 17 , wherein the transition metal dichalcogenide layer includes a plurality of monolayers.

19. The semiconductor device of claim 17 , wherein the fin feature includes a conductor material.

20. The semiconductor device of claim 17 , wherein the fin feature includes a dielectric material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Van Dal Mark
• Holland Martin Christopher
• Passlack Matthias

Classifications

• H01L29/1054

  Electricity · mapped topic

• H01L29/1606

  Electricity · mapped topic

• H01L27/10826

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic