Metal-oxide-semiconductor field effect transistors including a plurality of nanosheets

Patent metadata

Field	Value
Publication number	US-12396260-B2
Application number	US-202418645551-A
Country	US
Kind code	B2
Filing date	Apr 25, 2024
Priority date	Dec 24, 2020
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
preparing a semiconductor on insulator (SOI) substrate layer having a first region and a second region, the SOI substrate including a base substrate layer, an insulating substrate layer on the base substrate layer, and a cover substrate layer on the insulating substrate layer;
forming a substrate recess by removing the cover substrate layer and the insulating substrate layer in the second region;
forming an epi-substrate layer within the substrate recess in the second region, the epi-substrate layer and a portion of the base substrate layer in the second region constituting a semiconductor substrate layer;
forming a stacked structure of a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers on the SOI substrate layer and the semiconductor substrate layer, the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers being alternately stacked on the SOI substrate layer and the semiconductor substrate layer;
forming a plurality of first fin-type active areas in the first region, a plurality of second fin-type active areas in the second region, and a plurality of nanosheet stacked structures above the plurality of first fin-type active areas and the plurality of second fin-type active areas, by etching the stacked structure of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers, portions of the SOI substrate layer, and portions of the semiconductor substrate layer, wherein each of the plurality of nanosheet stacked structures comprising a plurality of nanosheets;
forming a plurality of first source/drain regions between adjacent nanosheet stacked structures in the first region; and
forming a plurality of second source/drain regions between adjacent nanosheet stacked structures in the second region.

2. The method of claim 1 , wherein each of the plurality of first source/drain regions extends into the SOI substrate layer, is in contact with the insulating substrate layer, and has a lower surface at a first vertical level.

3. The method of claim 2 , wherein each of the plurality of second source/drain regions extends into the semiconductor substrate layer and has a lower surface at a second vertical level that is farther from a main surface of the SOI substrate layer and a surface of the semiconductor substrate layer than the first vertical level.

4. The method of claim 1 , wherein each of the plurality of first source/drain regions extends through the cover substrate layer and into the insulating substrate layer.

5. The method of claim 1 , wherein each of the plurality of first source/drain regions extends through the cover substrate layer and contacts the insulating substrate layer without extending into the insulating substrate layer.

6. The method of claim 1 , wherein each of the plurality of first source/drain regions extends through the cover substrate layer and the insulating substrate layer, and wherein each of the plurality of first source/drain regions contacts the base substrate layer.

7. The method of claim 1 , further comprising:
forming a plurality of gate electrodes extending on the plurality of first fin-type active areas and the plurality of second fin-type active areas, each of the plurality of gate electrodes comprising a main gate unit above a respective one of the plurality of nanosheet stacked structures and a plurality of sub-gate units underneath each of the plurality of nanosheets of the respective one of the plurality of nanosheet stacked structures.

8. The method of claim 7 , further comprising:
forming a gate dielectric layer separating the plurality of gate electrodes and plurality of nanosheet stacked structures.

9. The method of claim 8 , further comprising:
forming a plurality of insulating spacers in the first region, the plurality of insulating spacers between the plurality of first source/drain regions and the plurality of nanosheets, the plurality of insulating spacers covering first and second ends of the plurality of sub-gate units with the gate dielectric layer therebetween.

10. The method of claim 9 , wherein, in the second region, the gate dielectric layer is arranged between the plurality of sub-gate units and the plurality of second source/drain regions, and wherein the gate dielectric layer directly contacts the plurality of sub-gate units and the plurality of second source/drain regions.

11. A method of manufacturing an integrated circuit device, the method comprising:
preparing a semiconductor on insulator (SOI) substrate layer having a first region and a second region, the SOI substrate including a base substrate layer, an insulating substrate layer on the base substrate layer, and a cover substrate layer on the insulating substrate layer;
forming a substrate recess by removing the cover substrate layer, the insulating substrate layer, and an upper portion of the base substrate layer in the second region;
forming an epi-substrate layer within the substrate recess in the second region, the epi-substrate layer and portion of the base substrate layer in the second region constituting a semiconductor substrate layer;
forming a first impurity region by injecting an impurity of a first conductivity into a portion of the SOI substrate layer in the first region;
forming a second impurity region by injecting an impurity of a second conductivity into a portion of the semiconductor substrate layer in the second region;
forming a stacked structure of a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers on the SOI substrate layer and the semiconductor substrate layer, the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers being alternately stacked on the SOI substrate layer and the semiconductor substrate layer;
forming a plurality of first fin-type active areas in the first region, a plurality of second fin-type active areas in the second region, and a plurality of nanosheet stacked structures above the plurality of first fin-type active areas and the plurality of second fin-type active areas, by etching the stacked structure of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers, portions of the SOI substrate layer, and portions of the semiconductor substrate layer, each of the plurality of nanosheet stacked structures comprising a plurality of nanosheets;
forming a plurality of first recess regions in the first region and a plurality of second recess regions in the second region by removing portions of the plurality of nanosheet stacked structures and portions of the plurality of sacrificial semiconductor layers; and
forming a plurality of first source/drain regions within the plurality of first recess regions and a plurality of second source/drain regions within the plurality of second recess regions.

12. The method of claim 11 , wherein a bottom of each of the plurality of first recess regions is at a first vertical level, and
wherein a bottom of each of the plurality of second recess regions is at a second vertical level different from the first vertical level.

13. The method of claim 12 , wherein each of the plurality of first source/drain regions extends into the SOI substrate layer and is in contact with the insulating substrate layer and has a lower surface at the first vertical level, and
wherein each of the plurality of second source/drain regions extends into the semiconductor substrate layer and has a lower surface at the second v

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Seokhyeon
• Park Junyoung
• Shin Woocheol
• Lee Seunghun

Classifications

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title