IFinFET

Patent metadata

Field	Value
Publication number	US-10236381-B2
Application number	US-201715607796-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	Sep 28, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a layered fin overlying a semiconductor substrate, wherein the layered fin comprises semiconductor layers and insulator layers, wherein two adjacent semiconductor layers are separated by a distance filled with the insulator layers;
a gate disposed over the layered fin;
a spacer surrounding a sidewall of the gate; and
source and drain regions located on the layered fin, the semiconductor layers being operatively coupled to the source and drain regions in a width direction, the width direction defined between one of the source and drain regions to another one of the source and drain regions;
wherein the insulator layer comprises a high-K dielectric material surrounded by a low-K dielectric material;
wherein a portion of the high-K dielectric material fills a central area of the distance in the width direction such that the portion of the high-K dielectric material is in contact with the two adjacent semiconductor layers and another portion of the low-K dielectric material fills a periphery of the distance on sides of the central area such that the another portion of the low-K dielectric material is in contact with the two adjacent semiconductor layers;
wherein a length of the semiconductor layers in the width direction equals a combined length of the high-K dielectric material and the low-K dielectric material in the width direction.

2. The semiconductor structure according to claim 1 , wherein the semiconductor layers comprise silicon.

3. The semiconductor structure according to claim 1 , wherein the semiconductor substrate is a silicon-on-insulator substrate.

4. The semiconductor structure according to claim 1 , wherein the semiconductor substrate is selected from the group consisting of silicon, germanium, and silicon germanium.

5. The semiconductor structure according to claim 1 , wherein the semiconductor layers comprise P-type dopants.

6. The semiconductor structure according to claim 1 , wherein the semiconductor layers comprise N-type dopants.

7. The semiconductor structure according to claim 1 , wherein the low-K dielectric material includes a dielectric constant of about 7 or less.

8. The semiconductor structure according to claim 1 , wherein the low-K dielectric material comprises silicon oxide, silicon nitride, boron nitride, silicon oxynitride, SiBCN, SiOCN, SiCN, SiCO, or a combination thereof.

9. The semiconductor structure according to claim 1 , wherein the high-K dielectric material includes a dielectric constant of greater than 7.

10. The semiconductor structure according to claim 9 , wherein the high-K dielectric material comprises metal oxides.

11. The semiconductor structure according to claim 1 , wherein the length of each of the semiconductor layers are equal in the width direction.

12. The semiconductor structure according to claim 1 , wherein the semiconductor layers comprise a first edge and a second edge in the width direction;
wherein a combination of the high-K dielectric material and the low-K dielectric in the width direction do not extend beyond the first and second edges of the semiconductor layers.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• H01L29/4983

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic