Integrated circuit devices having inter-device isolation regions and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10014300-B2
Application number	US-201715480669-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	Apr 29, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
at least one fin-type active region in a device region between first and second portions of an inter-device isolation region, the at least one fin-type active region protruding from a substrate in the device region and extending in a first direction;
a plurality of inner isolation layers in the device region, the plurality of inner isolation layers on sidewalls of the at least one fin-type active region and extending in the first direction; and
an outer isolation layer in an outer deep trench in the inter-device isolation region,
wherein at least one of the plurality of inner isolation layers extends away from the device region and toward the outer deep trench.

2. The integrated circuit device according to claim 1 , wherein the outer isolation layer has a sloped sidewall contacting an outermost inner isolation layer of the plurality of inner isolation layers, and
wherein the sloped sidewall is inclined such that a distance between the at least one fin-type active region and the sloped sidewall of the outer isolation layer is shorter as the sloped sidewall approaches the substrate.

3. The integrated circuit device according to claim 1 , wherein the outer isolation layer includes:
a fin-type insulating part contacting a sidewall of an outermost inner isolation layer and extending parallel to the at least one fin-type active region;
a lower insulating part extending along a surface of the substrate from the fin-type insulating part; and
an outer gap-fill insulating layer on the fin-type insulating part and on the lower insulating part and in the outer deep trench.

4. The integrated circuit device according to claim 3 , wherein the fin-type insulating part has a smaller width than a width of the at least one fin-type active region in a second direction crossing the first direction.

5. The integrated circuit device according to claim 3 , wherein each of the plurality of inner isolation layers includes an insulating liner on at least one of the sidewalls of the at least one fin-type active region, and
wherein the fin-type insulating part is in direct contact with the insulating liner of the outermost inner isolation layer.

6. The integrated circuit device according to claim 3 , wherein the fin-type insulating part has a sloped sidewall contacting the sidewall of the outermost inner isolation layer, and
wherein the sloped sidewall is inclined such that a spaced distance from the at least one fin-type active region is shorter as the fin-type insulating part is closer to the substrate.

7. The integrated circuit device according to claim 3 , wherein the fin-type insulating part has a larger width closer to the substrate in a second direction orthogonal to the first direction.

8. The integrated circuit device according to claim 1 , wherein the outer isolation layer includes two fin-type insulating parts spaced apart from each other with the device region therebetween, and
wherein the two fin-type insulating parts contact respective sidewalls of the inner isolation layers located at opposite outermost sides of the device region among the plurality of inner isolation layers and extend parallel to the at least one fin-type active region.

9. The integrated circuit device according to claim 1 , wherein the outer isolation layer includes a fin-type insulating part located at only a side of the device region, and
wherein the fin-type insulating part contacts a sidewall of an outermost inner isolation layer and extends parallel to the at least one fin-type active region.

10. An integrated circuit device comprising;
a fin-type active region in a device region of a substrate and extending in a first direction;
an inner isolation layer in a trench having a first depth, in the device region, the inner isolation layer on a sidewall of the fin-type active region; and
an outer isolation layer in an outer deep trench having a second depth deeper than the first depth, around the device region, the outer isolation layer contacting the inner isolation layer,
wherein the inner isolation layer extends away from the device region and toward the outer isolation layer,
wherein the outer isolation layer has a sloped sidewall contacting the inner isolation layer, and
wherein the sloped sidewall is inclined such that a distance between the fin-type active region and the sloped sidewall of the outer isolation layer is shorter as the sloped sidewall is closer to the substrate.

11. The integrated circuit device according to claim 10 , wherein the outer isolation layer includes a fin-type insulating part that contacts the inner isolation layer and extends along the first direction parallel to the fin-type active region.

12. The integrated circuit device according to claim 10 , wherein the outer isolation layer includes:
a fin-type insulating part having a sloped sidewall; and
a lower insulating part integrally connected to the fin-type insulating part, the lower insulating part extending along a surface of the substrate in the outer deep trench and having a thickness equal to or larger than a width of the fin-type insulating part.

13. The integrated circuit device according to claim 10 , wherein the outer isolation layer includes an outer gap-fill insulating layer in the outer deep trench,
the outer gap-fill insulating layer has a surface contacting the substrate and a sloped sidewall contacting the inner isolation layer, and
the sloped sidewall is at a higher level than the surface contacting the substrate.

14. An integrated circuit device comprising:
a device region on a substrate, wherein the device region is between a first portion and a second portion of an isolation region;
a plurality of fin-type active regions in the device region, each fin-type active region comprising sidewalls, each sidewall comprising thereon a respective inner isolation layer from a plurality of inner isolation layers; and
an outer isolation layer in an outer trench in the isolation region; wherein the plurality of fin-type active regions comprises an outermost fin-type active region, wherein the outermost fin-type active region corresponds with an outermost one of the inner isolation layers, and wherein the outermost one of the inner isolation layers extends away from the device region and into the isolation region.

15. The integrated circuit device according to claim 14 , wherein an inner sidewall is sloped such that a distance between the outer isolation layer and the outermost fin-type active region decreases as the inner sidewall approaches the substrate.

16. The integrated circuit device according to claim 14 , wherein each of the plurality of fin-type active regions extends above an upper surface of the outer isolation layer.

17. The integrated circuit device according to claim 14 , wherein the inner isolation layers are in a plurality of trenches, and wherein a first trench of the plurality of trenches is between a pair of the fin-type active regions.

18. The integrated circuit device according to claim 17 , wherein an outermost trench is between the outermost fin-type active region and the isolation region and is deeper than the first trench.

19. The integrated circuit device according to claim 14 , wherein the outer isolation layer comprises a fin-type insulating part, a lower insulating part integrally connected to the fin-type insulating part, and an outer gap-fill insulating layer on the lower insulating part.

20. The integrated circuit device according to claim 19 , wher

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cantoro Mirco
• Kwon Tae-Yong
• Park Jae-Young
• Hwang Dong-Hoon
• Lee Han-Ki
• YOU So-Ra

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L27/0924 Primary

  Electricity · mapped topic