Dielectric isolation in gate-all-around devices

Patent metadata

Field	Value
Publication number	US-10453736-B2
Application number	US-201715727974-A
Country	US
Kind code	B2
Filing date	Oct 9, 2017
Priority date	Oct 9, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first layer comprising a first sacrificial material, wherein the first layer is deposited, over a surface of a substrate;
a first set of layers of a second sacrificial material and a second set of layers of a channel material deposited over the first layer, wherein the first sacrificial material is etchable by a process at a first rate, wherein the second sacrificial material is etchable by the process at a second rate, and wherein the first rate is greater than the second rate;
a liner deposited in a first recess, wherein the first recess exposes a first connection end of a layer in the second set, wherein the first recess reaches into the substrate for at least a fraction of a total depth of the substrate;
an insulator material filling the first recess,
wherein etching is performed on the insulator material up to a stop depth, wherein the stop depth stops the etching at a height above the surface of the substrate,
wherein the liner is removed from at least the first connection end of the layer in the second set; and
an electrical connection formed with a source/drain structure using the first connection end of the layer in the second set, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

2. The semiconductor device of claim 1 , further comprising:
an epitaxy structure grown in electrical connection with the first connection end of the layer in the second set, wherein the epitaxy structure operates as the source/drain structure.

3. The semiconductor device of claim 1 , wherein the height above the substrate is zero.

4. The semiconductor device of claim 1 , wherein the height above the surface of the substrate reaches up to a substrate-facing surface of a bottom-most layer in the second set of layers.

5. The semiconductor device of claim 1 , wherein the first layer, the first set of layers, and the second set of layers together form a stack of layers, further comprising:
the first recess and a second recess formed by recessing the stack of layers, wherein the second recess exposes a second connection end of the layer in the second set, the second connection end being on an opposite side from the connection end, wherein the first recess and the second recess each reaches into the substrate for at least the fraction of the total depth of the substrate.

6. The semiconductor device of claim 1 , wherein a second layer immediately adjacent to the first layer comprises the second sacrificial material.

7. The semiconductor device of claim 1 , wherein a second layer immediately adjacent to the first layer comprises the channel material.

8. The semiconductor device of claim 1 , wherein the set of layers of the channel material includes a plurality of layers.

9. A method comprising:
depositing, over a surface of a substrate, a first layer comprising a first sacrificial material;
depositing, over the first layer, a first set of layers of a second sacrificial material and a second set of layers of a channel material, wherein the first sacrificial material is etchable by a process at a first rate, wherein the second sacrificial material is etchable by the process at a second rate, and wherein the first rate is greater than the second rate;
depositing a liner in a first recess, wherein the first recess exposes a first connection end of a layer in the second set, wherein the first recess reaches into the substrate for at least a fraction of a total depth of the substrate;
filling the first recess with an insulator material;
etching the insulator material up to a stop depth, wherein the stop depth stops the etching at a height above the surface of the substrate;
removing the liner from at least the first connection end of the layer in the second set; and
enabling the first connection end of the layer in the second set to form an electrical connection with a source/drain structure, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

10. The method of claim 9 , further comprising:
growing an epitaxy structure in electrical connection with the first connection end of the layer in the second set, wherein the epitaxy structure operates as the source/drain structure.

11. The method of claim 9 , wherein the height above the substrate is zero.

12. The method of claim 9 , wherein the height above the surface of the substrate reaches up to a substrate-facing surface of a bottom-most layer in the second set of layers.

13. The method of claim 9 , wherein the first layer, the first set of layers, and the second set of layers together form a stack of layers, further comprising:
recessing the stack of layers to form the first recess and a second recess, wherein the second recess exposes a second connection end of the layer in the second set, the second connection end being on an opposite side from the connection end, wherein the first recess and the second recess each reaches into the substrate for at least the fraction of the total depth of the substrate.

14. The method of claim 9 , wherein a second layer immediately adjacent to the first layer comprises the second sacrificial material.

15. The method of claim 9 , wherein a second layer immediately adjacent to the first layer comprises the channel material.

16. The method of claim 9 , wherein the set of layers of the channel material includes a plurality of layers.

17. A semiconductor fabrication system comprising a lithography component, the semiconductor fabrication system when operated on a wafer to fabricate a semiconductor device performing operations the comprising:
depositing, over a surface of a substrate, a first layer comprising a first sacrificial material;
depositing, over the first layer, a first set of layers of a second sacrificial material and a second set of layers of a channel material, wherein the first sacrificial material is etchable by a process at a first rate, wherein the second sacrificial material is etchable by the process at a second rate, and wherein the first rate is greater than the second rate;
depositing a liner in a first recess, wherein the first recess exposes a first connection end of a layer in the second set, wherein the first recess reaches into the substrate for at least a fraction of a total depth of the substrate;
filling the first recess with an insulator material;
etching the insulator material up to a stop depth, wherein the stop depth stops the etching at a height above the surface of the substrate;
removing the liner from at least the first connection end of the layer in the second set; and
enabling the first connection end of the layer in the second set to form an electrical connection with a source/drain structure, wherein a remaining portion of the insulator below the height and a remaining portion of the liner in the first recess electrically isolates the source/drain structure from the substrate and increases impedance in a path of a substrate current from the source/drain structure to the substrate.

18. The semiconductor fabrication system of claim 17 , further comprising:
growing an epitaxy structure in electrical connec

Assignees

• IBM

Inventors

• Chao Robin Hsin Kuo
• Cheng Kangguo
• Loubet Nicolas
• Montanini Pietro
• Xie Ruilong

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/40

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic