Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9972692-B2
Application number	US-201614994167-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Feb 10, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate having a main surface, and a fin-type active region projecting upright on the main surface and extending longitudinally in a first direction parallel to the main surface;
a gate line extending in a second direction across the fin-type active region;
a source/drain region at an upper part of the fin-type active region disposed to the side of the gate line, the source/drain region having a recess in an upper portion thereof;
a contact plug extending from within the recess, in a third direction perpendicular to the main surface of the substrate, so as to be disposed on the source/drain region; and
a metal silicide layer extending along surfaces of the source/drain region defining the recess, the metal silicide layer having a first portion covering a bottom surface of the contact plug and a second portion that is integral with the first portion and covers sides of a lower part of the contact plug, a thickness of the first portion in the third direction being different than a thickness of the second portion in a direction parallel to the main surface of the substrate.

2. The integrated circuit device of claim 1 , wherein the thickness of the second portion of the metal silicide layer is less than the thickness of the first portion of the metal silicide layer.

3. The integrated circuit device of claim 1 , wherein a thickness of the second portion of the metal silicide layer in the first direction is less than the thickness of the first portion of the metal silicide layer in the third direction.

4. The integrated circuit device of claim 1 , wherein the second portion of the metal silicide layer extends around the contact plug.

5. The integrated circuit device of claim 1 , wherein the second portion of the metal silicide layer has a thickness that decreases in the third direction away from the substrate.

6. The integrated circuit device of claim 1 , wherein the metal silicide layer contains a dopant.

7. The integrated circuit device of claim 6 , wherein the dopant includes at least one element selected from carbon group elements and inactive elements.

8. The integrated circuit device of claim 1 , wherein the metal silicide layer has a composition represented by MSixDy, wherein M is at least one metal, D is at least one element different from each metal M and Si, and 0<x≤3 and 0<y≤1.

9. The integrated circuit device of claim 8 , wherein M is at least one metal selected from the group consisting of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and
D is at least one element selected from the group consisting of Ge, C, Ar, Kr, and Xe.

10. The integrated circuit device of claim 1 , wherein the source/drain region has an uppermost surface that is farthest from the main surface of the substrate in the third direction,
the metal silicide layer has an uppermost part, and
the uppermost surface and the uppermost part of the metal silicide layer lie in a common plane.

11. The integrated circuit device of claim 1 , wherein the second portion of the metal silicide layer protrudes from a top surface of the fin-type active region in the third direction away from the substrate.

12. The integrated circuit device of claim 1 , wherein the first portion of the metal silicide layer is situated at a level between that of a lowermost surface of the gate line and a top surface of the fin-type active region.

13. The integrated circuit device of claim 1 , wherein a height of the contact plug is at least four times a height of the second portion of the metal silicide layer, as each measured from the bottom of the recess in the upper portion of the source/drain region.

14. The integrated circuit device of claim 1 , wherein the source/drain region comprises a crystalline semiconductor region and a local amorphous semiconductor region that is interposed between the metal silicide layer and the crystalline semiconductor region.

15. The integrated circuit device of claim 14 , wherein the local amorphous semiconductor region is interposed between the crystalline semiconductor region and the first portion of the metal silicide layer.

16. The integrated circuit device of claim 1 , further comprising:
a conductive barrier layer having a lower portion facing the metal silicide layer and extending around a lower portion of the contact plug, and an upper portion extending around an upper portion of the contact plug; and
a metal layer interposed between the metal silicide layer and the lower portion of the barrier layer and being of the same material as a metal constituting the metal silicide layer.

17. An integrated circuit device comprising:
a substrate spanning a first device region and a second device region of the device;
a first channel-type transistor in the first device region; and
a second channel-type transistor in the second device region,
wherein the first channel-type transistor and the second channel-type transistor each include:
a fin-type active region of the substrate extending longitudinally in a first direction,
a gate line extending in a second direction across the fin-type active region,
a source/drain region at an upper part of the fin-type active region and disposed to the side of the gate line, the source/drain region having a recess in an upper portion thereof,
a contact plug extending from within the recess, in a third direction perpendicular to the main surface of the substrate, so as to be disposed on the source/drain region, and
a metal silicide layer extending along surfaces of the source/drain region defining the recess,
wherein the metal silicide layer has a first portion covering a bottom surface of the contact plug and a second portion that is integral with the first portion and covers sides of a lower part of the contact plug, a thickness of the first portion in the third direction being different than a thickness of the second portion in a direction parallel to the main surface of the substrate, and
wherein a bottom of the metal silicide layer of the first channel-type transistor is situated at a level in the device different from that at which a bottom of the metal silicide layer of the second channel-type transistor is situated.

18. The integrated circuit device of claim 17 , wherein a height of the second portion of the metal silicide layer of the first channel-type transistor, as measured in the third direction, is different from that of the second portion of the metal silicide layer of the second channel-type transistor.

19. The integrated circuit device of claim 17 , wherein in each of the first channel-type transistor and the second channel-type transistor, the second portion of the metal silicide layer has a thickness that decreases the third direction away from the substrate.

20. The integrated circuit device of claim 17 , wherein in each of the first channel-type transistor and the second channel-type transistor,
the first portion and the second portion of the metal silicide layer each contain dopant of at least one element selected from the group consisting of Ge, C, Ar, Kr, and Xe.

Assignees

• Choi Jung Hun
• Eom Da Il
• Lee Sun Jung
• Jang Sung Uk
• Samsung Electronics Co Ltd

Inventors

• Choi Jung-Hun
• Eom Da-Il
• Lee Sun-Jung
• Jang Sung-Uk

Classifications

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H01L2029/7858

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic