Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12374596-B2
Application number	US-202217827992-A
Country	US
Kind code	B2
Filing date	May 30, 2022
Priority date	May 30, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs. The conductive balls are disposed on the substrate and electrically connected with the semiconductor die through the substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having a first surface and a second surface opposite to the first surface, and a ground plate embedded in the substrate;
at least one semiconductor die, disposed on the first surface of the substrate and electrically connected with the substrate;
a semiconductor frame structure, disposed on the substrate and surrounding the at least one semiconductor die, wherein the semiconductor frame structure includes a semiconductor body portion, a through hole penetrating through the semiconductor body portion, and a plurality of conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, the at least one semiconductor die is accommodated within the through hole and is spaced apart from a sidewall of the through hole with a distance, and at least one conductive TSV of the plurality of conductive TSVs is electrically connected with the ground plate;
a semiconductor cover structure, disposed on the semiconductor frame structure and on the at least one semiconductor die, wherein the semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the plurality of conductive TSVs; and
conductive balls, disposed on the second surface of the substrate and electrically connected with the at least one semiconductor die through the substrate.

2. The semiconductor package of claim 1 , wherein the plurality of conductive TSVs is located beside and around the at least one semiconductor die and the through hole.

3. The semiconductor package of claim 2 , wherein an air gap exists between the at least one semiconductor die and the sidewall of the through hole of the semiconductor frame structure.

4. The semiconductor package of claim 2 , further comprising a filling material disposed within the through hole and located between the at least one semiconductor die and the sidewall of the through hole of the semiconductor frame structure.

5. The semiconductor package of claim 2 , wherein the plurality of conductive TSVs penetrates through the semiconductor body portion and is exposed from the semiconductor body portion.

6. The semiconductor package of claim 1 , wherein the semiconductor cover structure includes a semiconductor main body portion, and the conductive grid pattern is inlaid in the semiconductor main body portion without penetrating through the semiconductor main body portion.

7. The semiconductor package of claim 1 , wherein the substrate includes contact pads and the plurality of conductive TSVs is connected with the contact pads.

8. The semiconductor package of claim 1 , wherein the plurality of conductive TSVs includes a metal material.

9. A semiconductor package, comprising:
a substrate having a ground plate embedded in the substrate;
a semiconductor die, disposed on the substrate and electrically connected with the substrate;
a semiconductor frame structure, disposed on the substrate and beside the semiconductor die, wherein the semiconductor frame structure includes a semiconductor body portion and a plurality of conductive through semiconductor vias (TSVs) penetrating through the semiconductor body portion;
a semiconductor cover structure, disposed on the semiconductor frame structure and on the semiconductor die, wherein the semiconductor cover structure includes a semiconductor main body portion and a conductive grid pattern inlaid in the semiconductor main body portion, and the conductive grid pattern is connected with the plurality of conductive TSVs, and the conductive grid pattern and the plurality of conductive TSVs connected to the conductive grid pattern are electrically grounded through the substrate; and
conductive balls, disposed on the substrate and electrically connected with the semiconductor die through the substrate,
wherein a gap exists between the semiconductor die and a sidewall of the semiconductor frame structure facing the semiconductor die and between the substrate and the semiconductor cover structure.

10. The semiconductor package of claim 9 , wherein a spreading span of the semiconductor cover structure is larger than an area of the semiconductor frame structure.

11. The semiconductor package of claim 9 , wherein a spreading span of the semiconductor cover structure is substantially equivalent to a spreading span of the semiconductor frame structure.

12. The semiconductor package of claim 9 , wherein the plurality of conductive TSVs includes a first metal material, and the conductive grid pattern includes a second metal material.

13. The semiconductor package of claim 9 , wherein the semiconductor frame structure includes a plurality of blocks, and the plurality of blocks are connected to form a ring-shaped frame structure surrounding the semiconductor die.

14. The semiconductor package of claim 9 , further comprising a filling material disposed between the semiconductor die and the sidewall of the semiconductor frame structure facing the semiconductor die and between the substrate and the semiconductor cover structure.

15. A semiconductor package, comprising:
a substrate having a ground plate embedded in the substrate;
a semiconductor die, disposed on the substrate and electrically connected with the substrate;
a semiconductor frame structure, disposed on the substrate and beside the semiconductor die, wherein the semiconductor frame structure includes semiconductor block portions and metallic through semiconductor vias (TSVs) penetrating through the semiconductor block portions;
an insulating filling material laterally wrapping the semiconductor block portions of the semiconductor frame structure and the semiconductor die;
a semiconductor cover structure, disposed on the semiconductor frame structure and on the semiconductor die, wherein the semiconductor cover structure includes a semiconductor body portion and a metallic grid pattern inlaid in the semiconductor body portion, and the metallic grid pattern is connected with the metallic TSVs, and the metallic grid pattern and the metallic TSVs connected to the metallic grid pattern are electrically grounded through the substrate; and
conductive balls, disposed on the substrate and electrically connected with the semiconductor die through the substrate.

16. The package of claim 15 , wherein a material of the metallic TSVs is different from a material of the metallic grid pattern.

17. The package of claim 15 , wherein the metallic TSVs include first metallic vias of a first size and second metallic vias of a second size different from the first size.

18. The package of claim 15 , wherein the metallic TSVs are connected with the metallic grid pattern and are electrically connected to the ground plate through contact pads in the substrate.

19. The package of claim 17 , wherein the metallic TSVs are interlinked with one another to form a chain wall structure.

20. The semiconductor package of claim 13 , wherein the plurality of conductive TSVs includes first metallic vias of a first size and second metallic vias of a second size different from the first size.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wei-Ming
• Lin Yu-Hung
• Tai Shih-Peng

Classifications

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title