Pattern fidelity enhancement

Patent metadata

Field	Value
Publication number	US-12334342-B2
Application number	US-202318361878-A
Country	US
Kind code	B2
Filing date	Jul 30, 2023
Priority date	Aug 29, 2017
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

First claim

What is claimed is:

1. A method, comprising:
forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process;
forming a resist layer over the hard mask layer;
patterning the resist layer to form a plurality of openings in the resist layer, wherein each of the openings is free of concave corners;
performing an opening expanding process to enlarge at least one of the openings in the resist layer, wherein after the performing of the opening expanding process, at least two of the openings merge;
transferring the openings in the resist layer to the hard mask layer; and
performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

2. The method of claim 1 , wherein the opening expanding process includes applying a first directional etching to inner sidewalls of the openings in the resist layer along a first direction.

3. The method of claim 2 , wherein the opening expanding process includes applying a second directional etching to the inner sidewalls of the openings in the resist layer along a second direction that is perpendicular to the first direction.

4. The method of claim 1 , wherein the treatment process is a gate cut process or a transistor threshold voltage tuning process.

5. The method of claim 1 , wherein after the performing of the opening expanding process, at least one of the openings in the resist layer remains separated from the merged openings.

6. The method of claim 1 , wherein prior to the performing of the opening expanding process, in a top view the one or more regions in the substrate are partially overlapped with the openings in the resist layer, and wherein after the performing of the opening expanding process, in the top view the one or more regions in the substrate are fully overlapped with the openings in the resist layer.

7. The method of claim 1 , wherein after the performing of the opening expanding process, at least three of the openings merge.

8. A method, comprising:
forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process;
forming a resist layer over the hard mask layer;
patterning the resist layer to form a plurality of openings in the resist layer, wherein each of the openings is free of concave corners;
transferring the openings in the resist layer to the hard mask layer;
performing an opening expanding process to enlarge at least one of the openings in the hard mask layer, wherein after the performing of the opening expanding process, at least two of the openings merge; and
performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

9. The method of claim 8 , wherein the opening expanding process includes applying a first directional etching to inner sidewalls of the openings in the hard mask layer along a first direction.

10. The method of claim 9 , wherein the opening expanding process includes applying a second directional etching to the inner sidewalls of the openings in the hard mask layer along a second direction that is perpendicular to the first direction.

11. The method of claim 8 , wherein the treatment process is a gate cut process or a transistor threshold voltage tuning process.

12. The method of claim 8 , wherein after the performing of the opening expanding process, at least one of the openings in the hard mask layer remains separated from the merged openings.

13. The method of claim 8 , wherein prior to the performing of the opening expanding process, in a top view the one or more regions in the substrate are partially overlapped with the openings in the hard mask layer, and wherein after the performing of the opening expanding process, in the top view the one or more regions in the substrate are fully overlapped with the openings in the hard mask layer.

14. The method of claim 8 , wherein the one or more regions are active regions of transistors and the treatment process includes an ion implantation.

15. A method, comprising:
forming a resist layer over a substrate, the substrate having one or more regions to receive a treatment process;
patterning the resist layer to form a plurality of openings in the resist layer, wherein each of the openings is free of concave corners;
performing an opening expanding process to enlarge at least one of the openings in the resist layer, wherein after the performing of the opening expanding process, at least two of the openings merge; and
performing the treatment process to the one or more regions in the substrate through the openings in the resist layer.

16. The method of claim 15 , wherein the opening expanding process includes applying a first directional etching to inner sidewalls of the openings in the resist layer along a first direction.

17. The method of claim 16 , wherein the opening expanding process includes applying a second directional etching to the inner sidewalls of the openings in the resist layer along a second direction that is perpendicular to the first direction.

18. The method of claim 15 , wherein the treatment process is a gate cut process or a transistor threshold voltage tuning process.

19. The method of claim 15 , wherein prior to the performing of the opening expanding process, in a top view the one or more regions in the substrate are partially overlapped with the openings in the resist layer, and wherein after the performing of the opening expanding process, in the top view the one or more regions in the substrate are fully overlapped with the openings in the resist layer.

20. The method of claim 15 , wherein after the at least two of the openings are merged, the merged openings are free of concave corners.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Yu-Tien
• Yeh Ya-Wen
• Lin Wei-Liang
• Chang Ya Hui
• Yen Yung-Sung
• Wu wei-hao
• Lin Li-Te
• Liu Ru-Gun
• Chen Kuei-Shun

Classifications

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P76/204 Primary

  of organic photoresist masks · CPC title