Pattern fidelity enhancement with directional patterning technology

Patent metadata

Field	Value
Publication number	US-10658184-B2
Application number	US-201715474522-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Dec 15, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

First claim

What is claimed is:

1. A method for semiconductor manufacturing, comprising:
providing a substrate and a patterning layer over the substrate, wherein the patterning layer has substantial uniform thickness across the entire substrate;
removing a first portion of the patterning layer to form a hole in the patterning layer;
applying a first directional etching along a first direction to two opposing inner sidewalls of the hole to remove a second portion of the patterning layer; and
applying a second directional etching along a second direction to another two opposing inner sidewalls of the hole to remove a third portion of the patterning layer, wherein the second direction is different from the first direction.

2. The method of claim 1 , wherein the patterning layer includes a photoresist.

3. The method of claim 1 , wherein the patterning layer includes a hard mask layer.

4. The method of claim 1 , wherein the second direction is perpendicular to the first direction.

5. The method of claim 1 , further comprising:
etching the substrate through the hole.

6. The method of claim 1 , wherein the first and second directional etching are applied simultaneously.

7. The method of claim 1 , wherein the hole is a substantially rectangular pattern.

8. The method of claim 1 , wherein the hole is a substantially L-shaped pattern.

9. A method for semiconductor manufacturing, comprising:
providing a substrate;
forming a resist layer over the substrate;
applying a first exposure to a first portion of the resist layer with a first exposure energy higher than an exposure threshold of the resist layer, wherein the first portion surrounds four sides of a first rectangular region;
applying a second exposure to a second portion of the resist layer with a second exposure energy higher than the exposure threshold of the resist layer, wherein the second portion includes a first right-angle corner extending into the first rectangular region; and
developing the resist layer to form a resist pattern corresponding to the first rectangular region minus the second portion.

10. The method of claim 9 , wherein the second portion includes a second right-angle corner extending into the first rectangular region.

11. The method of claim 10 , wherein the first and second right-angle corners extend into the first rectangular region from two diagonally opposite corners of the first rectangular region.

12. The method of claim 10 , wherein the first and second right-angle corners extend into the first rectangular region from two opposite corners of the first rectangular region along a same side of the first rectangular region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Yu-Tien
• Hung Chi-Cheng
• Lin Chin-Hsiang
• Wang Chien-Wei
• Chang Ching-Yu
• Ting Chih-Yuan
• Chen Kuei-Shun
• Liu Ru-Gun
• Lin Wei-Liang
• Chang Ya Hui
• Lung Yuan-Hsiang
• Chen Yen-Ming
• Yen Yung-Sung

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P30/222 Primary

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L21/26586 Primary

  Electricity · mapped topic