Directional patterning methods

Patent metadata

Field	Value
Publication number	US-10049918-B2
Application number	US-201615395310-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Sep 29, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

First claim

What is claimed is:

1. A method comprising:
forming a patterned hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature; and
performing a surface directional etching process to modify a horizontal profile of the hard mask feature, wherein:
the surface directional etching process directs etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, and
the surface directional etching process does not etch in a vertical direction.

2. The method of claim 1 , further comprising forming an integrated circuit feature that corresponds with the hard mask feature.

3. The method of claim 1 , wherein the surface directional etching process directs the etching species towards a horizontal surface of the wafer at an angle θ that is less than about 10° relative to a horizontal plane that is substantially parallel to the horizontal surface.

4. The method of claim 1 , wherein the surface directional etching process further directs the etching species in an in-plane direction.

5. The method of claim 4 , wherein the hard mask feature is an opening, and further wherein the surface directional etching process is implemented with the in-plane direction along sidewalls of the opening to increase a horizontal dimension of the opening.

6. The method of claim 4 , wherein the hard mask feature is an opening and an end-to-end space is defined between the opening and an adjacent opening, wherein the surface directional etching process is implemented with the in-plane direction along sidewalls of the opening and sidewalls of the adjacent opening to decrease the end-to-end space.

7. The method of claim 4 , wherein the hard mask feature is a line having a line width roughness, and further wherein the surface directional etching process is implemented with the in-plane direction along edges of the line to reduce the line width roughness.

8. The method of claim 4 , wherein the hard mask feature is an opening having an end portion, and further wherein the surface directional etching process is implemented with the in-plane direction oblique to the end portion to reshape the end portion.

9. A method comprising:
forming a patterned hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature; and
performing a surface directional etching process to modify a horizontal profile of the hard mask feature, wherein:
the surface directional etching process directs etching species in an in-plane direction and a substantially horizontal direction relative to a horizontal surface of the wafer,
the hard mask feature is an opening, and
the surface directional etching process is implemented with the in-plane direction oblique to portions of the opening, thereby transforming the opening into an oblique opening.

10. A method comprising:
forming a patterned hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature; and
performing a surface directional etching process to modify a horizontal profile of the hard mask feature, wherein:
the surface directional etching process directs etching species in in an in-plane direction and a substantially horizontal direction relative to a horizontal surface of the wafer,
the hard mask feature is a circular-shaped via opening used to define a square-shaped via, and
the surface directional etching process is implemented with the in-plane direction along sidewalls of the circular-shaped via opening, thereby transforming the circular-shaped opening into an oval-shaped opening used to define a slot-shaped via.

11. A method comprising:
performing a lithography process to form a patterned hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic;
tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and
forming an integrated circuit (IC) feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic, wherein the horizontally-defined characteristic is a minimum characteristic achievable by the lithography process, and the modified horizontally-defined characteristic is smaller than the minimum characteristic achievable by the lithography process.

12. The method of claim 11 , wherein the horizontally-defined characteristic is a line width roughness associated with the hard mask feature, an end-to-end spacing associated with the hard mask feature, or a line end profile associated with the hard mask feature.

13. The method of claim 11 , wherein modifying the horizontally-defined characteristic of the hard mask feature includes forming an oblique opening.

14. The method of claim 11 , wherein modifying the horizontally-defined characteristic of the hard mask feature includes increasing a length or a width of the hard mask feature.

15. A method comprising:
forming a patterned material layer over a substrate, wherein an opening is defined in the patterned material layer;
forming a hard mask layer over the patterned material layer;
performing a surface directional implantation process on the hard mask layer, wherein the hard mask layer includes an implanted portion and a non-implanted portion;
removing the non-implanted portion of the hard mask layer; and
performing an etching process to modify a horizontal profile of the opening, wherein the implanted portion of the hard mask layer protects a portion of the patterned material layer that defines the opening during the etching process.

16. The method of claim 15 , wherein surface directional implantation process implants doping species along sidewalls of the opening extending in a single direction.

17. The method of claim 15 , wherein the performing the surface directional implantation process includes modifying an etching characteristic of the hard mask layer, such that the implanted portion has a different etching resistance than the non-implanted portion.

18. The method of claim 15 , wherein the etching process is a surface directional etching process that directs etching species in a substantially horizontal direction relative to a horizontal surface of the substrate.

19. The method of claim 15 , wherein the implanted portion of the hard mask layer forms a sidewall mask along a sidewall of the opening.

20. The method of claim 1 , wherein the surface directional etching process selectively etches the patterned hard mask layer relative to the wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Chi-Cheng
• Liu Ru-Gun
• Lin Wei-Liang
• Yu Ta-Ching
• Yen Yung-Sung
• Fang Ziwei
• Gau Tsai-Sheng
• Lin Chin-Hsiang
• Chen Kuei-Shun

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P30/40

  into insulating materials · CPC title