Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition

Patent metadata

Field	Value
Publication number	US-2016118296-A1
Application number	US-201514874307-A
Country	US
Kind code	A1
Filing date	Oct 2, 2015
Priority date	Oct 25, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one dual damascene structure formed within a dielectric material over the substrate, the at least one dual damascene structure including a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material such that the underlying conductive material is exposed at a bottom of the opening; exposing the at least one dual damascene structure to a flowable film for a period of time that is less than a time required for nucleation of the flowable film to occur on the underlying conductive material and that is greater than a time required for nucleation of the flowable film to occur on exposed surfaces of the dielectric material, such that the flowable film deposits on exposed surfaces of the dielectric material in the opening without depositing on the underlying conductive material exposed at the bottom of the opening, wherein the flowable film deposited on the exposed surfaces of the dielectric material forms a sealing barrier layer; performing a cleaning process on the substrate, with structures formed thereon, to remove material residues left over from the deposition of the flowable film to form the sealing barrier layer; and performing an electroless deposition process to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench, wherein the electroless deposition process initiates on the underlying conductive material exposed at the bottom of the opening.

2 . The method of claim 1 , further comprising:
stopping of exposing the at least one dual damascene structure to the flowable film after the period of time; and repeating of exposing the at least one dual damascene structure to the flowable film for the period of time prior to performing the electroless deposition process.

3 . The method of claim 1 , wherein the flowable film is either a nitride film or a carbide film.

4 . The method of claim 1 , further comprising:
prior to exposing the at least one dual damascene structure to the flowable film for the period of time, exposing the at least one dual damascene structure to a pre-treatment plasma to decrease the time required for nucleation of the flowable film to occur on exposed surfaces of the dielectric material.

5 . The method of claim 4 , wherein the pre-treatment plasma is formed from a pre-treatment process gas including one or more of a hydrogen-containing compound, a nitrogen-containing compound, and an oxygen-containing compound.

6 . The method of claim 1 , further comprising:
after exposing the at least one dual damascene structure to the flowable film for the period of time, performing a post-treatment process to affect a change in the flowable film that was deposited, wherein the change is one or more of densification, chemical conversion, and physical conversion.

7 . The method of claim 6 , wherein the post-treatment process includes exposure of the flowable film that was deposited to one or more of an inert plasma, a reactive plasma, a thermal annealing process, and radiative energy, the radiative energy being one or more of ultra-violet radiation, infra-red radiation, and microwave radiation.

8 . The method of claim 1 , further comprising:
depositing a barrier material to cover exposed surfaces of the trench and the metallic material that fills the opening; depositing a liner material to cover exposed surfaces of the barrier material; depositing a copper seed layer to cover exposed surfaces of the liner material; and filling a remainder of the trench with copper by performing either a copper electroplating process or a copper electroless deposition process.

9 . A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one dual damascene structure formed within a dielectric material over the substrate, the at least one dual damascene structure including a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material such that the underlying conductive material is exposed at a bottom of the opening; forming an amorphous carbon barrier layer on each sidewall of the opening without covering the underlying conductive material exposed at the bottom of the opening; performing a cleaning process on the substrate, with structures formed thereon, to remove material residues left over from formation of the amorphous carbon barrier layer; and performing an electroless deposition process to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench, wherein the electroless deposition process initiates on the underlying conductive material exposed at the bottom of the opening.

10 . The method of claim 9 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening includes exposing the at least one dual damascene structure to a deposition plasma.

11 . The method of claim 10 , wherein the deposition plasma is formed from a deposition gas that includes a hydrocarbon and an oxygen free inert diluent.

12 . The method of claim 10 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening further includes exposing the amorphous carbon barrier layer to a conditioning plasma.

13 . The method of claim 12 , wherein the conditioning plasma is formed from a conditioning gas that includes hydrogen and that is essentially free of any hydrocarbon compound.

14 . The method of claim 9 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening includes performing a plasma-enhanced chemical vapor deposition process, or performing a deposition process that utilizes an inductively-coupled plasma, or performing a deposition process that utilizes a capacitively-coupled plasma, or performing a deposition process that utilizes a transformer-coupled plasma, or performing a deposition process that utilizes a remotely generated plasma relative to the substrate.

15 . The method of claim 9 , further comprising:
depositing a barrier material to cover exposed surfaces of the trench and the metallic material that fills the opening; depositing a liner material to cover exposed surfaces of the barrier material; depositing a copper seed layer to cover exposed surfaces of the liner material; and filling a remainder of the trench with copper by performing either a copper electroplating process or a copper electroless deposition process.

16 . A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one dual damascene structure formed within a dielectric material over the substrate, the at least one dual damascene structure including a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material such that the underlying conductive material is exposed at a bottom of the opening; forming a self-assembled monolayer of an amino group on each sidewall of the opening without covering the underlying conductive material exposed at the bottom of the opening; performing a cleaning process on the substrate, with structures formed thereon, to remove material residues left over from formation of the self-assembled monolayer; and performing an electroless deposition process to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench, wherein the electroless deposition process initiates on the underlying conductive material exposed at the bottom of the opening.

Assignees

• Lam Res Corp

Inventors

• Kolics Artur
• Lee William T
• Zhao Larry
• Wong Derek
• Nalla Praveen
• Ashtiani Kaihan
• Van Cleemput Patrick A
• Dordi Yezdi

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title