Interconnect structure without barrier layer on bottom surface of via
US-2025279315-A1 · Sep 4, 2025 · US
Ho Chien-Hsin is listed as an inventor on 12 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ho Chien-Hsin |
| Total patents | 12 |
| First publication | Jan 15, 2015 |
| Latest publication | Sep 4, 2025 |
Publications ranked by popularity score, then publication date.
US-2025279315-A1 · Sep 4, 2025 · US
US-12308282-B2 · May 20, 2025 · US
US-2025113499-A1 · Apr 3, 2025 · US
US-2025054810-A1 · Feb 13, 2025 · US
US-2024088042-A1 · Mar 14, 2024 · US
US-2022262675-A1 · Aug 18, 2022 · US
US-11322391-B2 · May 3, 2022 · US
US-2020035546-A1 · Jan 30, 2020 · US
US-10453740-B2 · Oct 22, 2019 · US
US-2019006230-A1 · Jan 3, 2019 · US
Latest publications not already listed above.
US-9842767-B2 · Dec 12, 2017 · US
US-2015017799-A1 · Jan 15, 2015 · US
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 11 |
| Taiwan Semiconductor Mfg | 1 |
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/425 | 11 |
| H10W20/057 | 10 |
| H10W20/035 | 9 |
| H10W20/036 | 9 |
| H01L21/76846 | 9 |