Interconnect formation with chamferless via, and related interconnect

Patent metadata

Field	Value
Publication number	US-10566231-B2
Application number	US-201815966032-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Apr 30, 2018
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

First claim

What is claimed is:

1. A method of forming an interconnect for an integrated circuit (IC), the method comprising:
forming a first ILD layer over an interconnect layer, the interconnect layer including a conductive structure therein under an interconnect layer etch stop layer (ESL);
forming an interlayer dielectric etch stop layer (ILD ESL) extending between the first interlayer dielectric (ILD) layer and a second ILD layer, wherein the ILD ESL has an etch rate that is at least five times slower than the first ILD layer and the second ILD layer; and
forming a unitary via-wire conductive structure having a chamferless via portion thereof in the first ILD layer and a wire trench portion thereof in the second ILD layer over the first ILD layer, the unitary via-wire structure formed by:
forming a dual damascene (DD) hard mask over the second ILD layer, wherein the DD hard mask includes a patterned wire trench hard mask layer over the second ILD layer, a mask barrier layer over the patterned wire trench hard mask layer, and a patterned via opening hard mask layer over the mask barrier layer;
forming a patterned, mask etch stop layer (ESL) over the mask barrier layer and under the patterned via trench hard mask layer,
etching a preliminary via opening through the second ILD layer to the ILD ESL using the DD hard mask,
removing the ILD ESL at a bottom of the preliminary via opening, creating a via ESL opening through the ILD ESL,
etching to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening, wherein the via ESL opening in the ILD ESL defines the via opening in the first ILD layer as the chamferless via opening, and
depositing a barrier liner over the via-wire opening, and depositing a conductor in the via-wire opening and planarizing to form the unitary via-wire conductive structure coupled to the conductive structure,

wherein the chamferless via portion extends through the ILD ESL.

2. The method of claim 1 , further comprising, prior to the etching the wire trench opening and the via opening, removing the mask barrier layer, exposing the patterned wire trench hard mask layer.

3. The method of claim 1 , further comprising, prior to the forming the unitary via-wire conductive structure, removing any remaining interconnect layer ESL in the via opening to expose an upper surface of the conductive structure in the interconnect layer.

4. The method of claim 3 , wherein the interconnect layer ESL includes a selected one of an oxygen-doped silicon carbide layer (SiC:O) and a nitrogen-doped silicon carbide (SiC:N), over an aluminum oxynitride (AlON) layer, and
wherein the etching to form the via opening removes the selected SiC:O or SiC:N layer in a bottom of the via opening exposing the AlON layer, and the removing any remaining interconnect layer ESL removes the AlON layer in the bottom of the via opening, exposing the upper surface of the conductive structure.

5. The method of claim 1 , wherein the first ILD layer includes octamethylcyclotetrasiloxane (OMCTS) 2.7, and the second ILD layer includes OMCTS 2.4.

6. The method of claim 1 , wherein the ILD ESL has a thickness of less than 5nanometers.

7. The method of claim 1 , wherein the ILD ESL includes aluminum oxynitride (AlON).

8. A method of forming an interconnect of an integrated circuit (IC), the method comprising:
forming a first interlayer dielectric (ILD) layer over an interconnect layer, the interconnect layer including a conductive structure therein under an interconnect layer etch stop layer (ESL);
forming an aluminum oxynitride (AlON) etch stop layer (ESL) over the first ILD layer, the AlON ESL having a thickness of less than 5 nanometers;
forming a second interlayer dielectric (ILD) layer over the AlON ESL;
forming a dual damascene (DD) hard mask over the second ILD layer, the DD hard mask including: a patterned wire trench hard mask layer over the second ILD layer, a mask barrier layer over the patterned wire trench hard mask layer, and a patterned via opening hard mask layer over the mask barrier layer;
etching a preliminary via opening through the mask barrier layer, the patterned hard mask layer and the second ILD layer to the AlON ESL;
removing the AlON ESL at a bottom of the preliminary via opening, creating a via ESL opening in the AlON ESL;
removing the mask barrier layer, exposing the patterned wire trench hard mask layer;
etching to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, wherein the via ESL opening in the AlON ESL defines the via opening in the first ILD layer as a chamferless via opening;
removing any remaining interconnect layer ESL in the via opening to expose an upper surface of the conductive structure in the interconnect layer; and
forming a unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening.

9. The method of claim 8 , further comprising forming a patterned, mask aluminum oxynitride (AlON) etch stop layer (ESL) over the mask barrier layer and under the patterned via trench hard mask layer.

10. The method of claim 8 , wherein the forming the unitary via-wire conductive structure includes depositing a barrier liner over the via-wire opening, depositing a conductor in the via-wire conductive structure and planarizing.

11. The method of claim 8 , wherein the interconnect layer ESL includes an oxygen-doped silicon carbide (SiC:N) layer over an aluminum oxynitride (AlON) layer, and
wherein the etching to form the via opening removes the SiC:N layer in a bottom of the via opening exposing the AlON layer, and the removing any remaining interconnect layer ESL removes the AlON layer in the bottom of the via opening, exposing the upper surface of the conductive structure.

12. The method of claim 11 , wherein the removing the AlON ESL and the removing the AlON layer of the interconnect layer ESL each include performing one of a reactive ion etch (RIE) and a wet etch.

13. The method of claim 8 , wherein the mask barrier layer includes a spin-on hard mask (SOH) layer.

14. The method of claim 8 , wherein the first ILD layer includes octamethylcyclotetrasiloxane (OMCTS) 2.7, and the second ILD layer includes OMCTS 2.4.

Assignees

• Globalfoundries Inc

Inventors

• O'Toole Martin J
• Penny Christopher J
• Choo Jae O
• Da Silva Adam L
• Child Craig
• Spooner Terry A
• Chen Hsueh-Chung
• O'Brien Brendan
• Donegan Keith P

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/088 Primary

  involving partial etching of via holes · CPC title

• H10W20/087 Primary

  involving multiple stacked pre-patterned masks · CPC title

• H01L21/76813 Primary

  Electricity · mapped topic