Three-dimensional memory device with divided drain select gate lines and method for forming the same

Patent metadata

Field	Value
Publication number	US-12302560-B2
Application number	US-202217568630-A
Country	US
Kind code	B2
Filing date	Jan 4, 2022
Priority date	Dec 13, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

First claim

What is claimed is:

1. A memory device, comprising:
a stack structure over a substrate;
a channel structure extending in the stack structure;
a dielectric layer over the channel structure, the dielectric layer comprising a first dielectric material;
a drain-select gate (DSG) cut structure comprising a second dielectric material different from the first dielectric material; and
a contact over the channel structure, the contact extending into the dielectric layer and contacting the DSG cut structure,
wherein:
the DSG cut structure is in contact with the channel structure and one or more conductive layers of the stack structure and in no contact with another channel structure in a cross-section of the channel structure perpendicular to a lateral direction along which the DSG cut structure extends; and
a bottommost surface of the contact is in direct contact with a top surface of a channel plug over the channel structure.

2. The memory device of claim 1 , wherein the DSG cut structure is in contact with the channel structure and a DSG in a plurality of conductive layers.

3. The memory device of claim 1 , wherein an etching selectivity of the first dielectric material over the second dielectric material is greater than 1.

4. The memory device of claim 1 , wherein the first dielectric material comprises silicon oxide and the second dielectric material comprises silicon nitride.

5. The memory device of claim 1 , wherein the DSG cut structure does not comprise silicon oxide.

6. The memory device of claim 5 , where the DSG cut structure comprises silicon nitride.

7. The memory device of claim 1 , wherein the DSG cut structure comprises a liner silicon oxide layer and a silicon nitride layer surrounded by the liner silicon oxide layer.

8. The memory device of claim 7 , wherein the DSG cut structure comprises a silicon nitride layer surrounded by the liner silicon oxide layer, and a filler layer surrounded by the silicon nitride layer.

9. The memory device of claim 8 , wherein the filler layer comprises an airgap.

10. The memory device of claim 1 , further comprises a pair of source contact structures extending in the lateral direction and a memory block between the pair of source contact structures, the memory block comprising a plurality of memory cells in a plurality of channel structures between the source contact structures,
wherein
the memory block comprises a pair of strings adjacent to each other, each of the strings comprising a plurality of rows of channel structures in the lateral direction, and
the DSG cut structure, extending in the lateral direction, is between the pair of strings and is in contact with at least one of the rows of the channel structures.

11. The memory device of claim 10 , wherein each of the strings comprises four rows of channel structures.

12. The memory device of claim 1 , wherein a top surface of the dielectric layer is coplanar with an entire top surface of the DSG cut structure.

13. The memory device of claim 1 , wherein the channel plug arranged at a top of the channel structure is in contact with a sidewall of the DSG cut structure, and an entire top surface of the DSG cut structure being higher than the top surface of the channel plug and the bottommost surface of the contact.

14. The memory device of claim 1 , wherein the contact is in no contact with a sidewall of the channel plug, and the sidewall of the channel plug is in contact with a sidewall of the DSG cut structure.

15. The memory device of claim 1 , wherein a first bottom surface of the contact in contact with the channel plug is lower than a second bottom surface of the contact in contact with the DSG cut structure.

16. A memory system, comprising:
a memory device configured to store data, the memory device comprising:
a stack structure over a substrate,
a channel structure extending in the stack structure,
a dielectric layer over the channel structure, the dielectric layer comprising a first material silicon oxide,
a drain-select gate (DSG) cut structure extending through the dielectric layer and comprising a second material, and
a contact over the channel structure, the contact extending into the dielectric layer and contacting the DSG cut structure,
wherein;
the DSG cut structure is in contact with the channel structure and one or more conductive layers of the stack structure and in no contact with another channel structure in a cross-section of the channel structure perpendicular to a lateral direction along which the DSG cut structure extends; and
a bottommost surface of the contact is in direct contact with a top surface of a channel plug over the channel structure

a memory controller coupled to the memory device and configured to control operations of the channel structure.

17. The memory device of claim 16 , wherein a sidewall of the DSG cut structure is in contact with a sidewall of the channel plug arranged at a top of the channel structure.

18. A memory device, comprising:
a stack structure;
a channel structure extending in the stack structure;
a dielectric layer over the channel structure, the dielectric layer comprising a first material;
a drain-select gate (DSG) cut structure; and
a contact over the channel structure, the contact extending into the dielectric layer and contacting the DSG cut structure,
wherein:
the DSG cut structure comprises a second material different from the first material; and
a bottommost surface of the contact is in direct contact with a top surface of a channel plug over the channel structure, and a sidewall of the channel plug is in direct contact with a sidewall of the DSG cut structure.

19. The memory device of claim 18 , wherein a top surface of the dielectric layer is coplanar with an entire top surface of the DSG cut structure.

20. The memory device of claim 18 , wherein the first material comprises a dielectric material.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Di
• Gu Yan
• Xia Zhiliang
• Zhou Wenxi
• Huo Zongliang

Classifications

• H10D64/679

  comprising air gaps · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title