Three-dimensional memory device including replacement crystalline channels and methods of making the same

Patent metadata

Field	Value
Publication number	US-10868025-B2
Application number	US-201816200115-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Nov 26, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
source-level material layers comprising a source contact layer including a doped crystalline semiconductor material;
an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers;
a memory opening extending through the alternating stack and through the source contact layer; and
a memory opening fill structure including a memory film and a vertical semiconductor channel laterally surrounded by the memory film, wherein a semiconductor-to-semiconductor interface between the vertical semiconductor channel and the source contact layer is laterally offset farther away from a vertical axis passing through a geometrical center of the memory opening fill structure than a semiconductor-to-dielectric interface between the vertical semiconductor channel and the memory film is from the vertical axis.

2. The three-dimensional memory device of claim 1 , wherein:
a predominant portion of grain boundaries of the source contact layer extend along lateral directions; and
an average lateral dimension of the grain boundaries of the source contact layer is at least a thickness of the source contact layer that is a vertical distance between a top surface of the source contact layer and a bottom surface of the source contact layer.

3. The three-dimensional memory device of claim 2 , wherein crystallographic orientations of grains of the vertical semiconductor channel are aligned to crystallographic orientations of the grains of the source contact layer at the semiconductor-to-semiconductor interface.

4. The three-dimensional memory device of claim 1 , wherein the vertical semiconductor channel contacts a bottom surface of the memory film.

5. The three-dimensional memory device of claim 4 , wherein the bottom surface of the memory film is a tapered annular concave surface that vertically protrude further downward at a bottom periphery of an inner sidewall of the memory film than at a bottom periphery of an outer sidewall of the memory film.

6. The three-dimensional memory device of claim 1 wherein the memory film comprises a layer stack including:
a blocking dielectric contacting the alternating stack;
a charge storage layer contacting the blocking dielectric; and
a tunneling dielectric contacting the charge storage layer and the vertical semiconductor channel.

7. The three-dimensional memory device of claim 6 , wherein the memory opening fill structure comprises a bottom dielectric cap that comprises:
a first dielectric layer having a same composition and a same thickness as the blocking dielectric;
a second dielectric layer having a same composition and a same thickness as the charge storage layer; and
a third dielectric layer having a same composition and a same thickness as the tunneling dielectric and contacting a bottommost surface of the vertical semiconductor channel.

8. The three-dimensional memory device of claim 1 , wherein the vertical semiconductor channel fills at least a volume that is laterally bounded by the memory film and located between a first horizontal plane including a bottom surface of a bottommost one of the electrically conductive layers and a second horizontal plane including a top surface of a topmost one of the electrically conductive layers.

9. The three-dimensional memory device of claim 1 , wherein the semiconductor-to-semiconductor interface comprises a cylindrical interface that vertically extends from a first plane including a horizontal top surface of the source contact layer to a second plane including a horizontal bottom surface of the source contact layer.

10. The three-dimensional memory device of claim 1 , wherein the source-level material layers comprise:
a source-level lower dielectric layer contacting a bottom surface of the source contact layer; and
at least one source-level upper dielectric layer contacting a top surface of the source contact layer.

11. The three-dimensional memory device of claim 10 , wherein:
the source-level lower dielectric layer comprises a silicon nitride layer; and
the at least one source-level upper dielectric layer comprises a layer stack of a first source-level upper dielectric layer and a second source-level upper dielectric layer that overlies the silicon nitride layer.

12. The three-dimensional memory device of claim 1 , wherein:
the vertical semiconductor channel includes a void through which the vertical axis passing through the geometrical center of the memory opening fill structure extends; and
the void is located between a horizontal plane including a bottom surface of the source contact layer and a horizontal plane including a top surface of the source contact layer.

13. The three-dimensional memory device of claim 1 , further comprising:
a substrate underlying the source-level material layers; and
at least one dielectric layer including metal interconnect structures and located between the substrate and the source-level material layers,
wherein the memory opening fill structure and portions of the electrically conductive layers that are proximal to the memory opening fill structure comprise a vertical NAND string.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhou Fei
• RAJASHEKHAR Adarsh
• Sharangpani Rahul
• Makala Raghuveer S

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic