Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same

Patent metadata

Field	Value
Publication number	US-10790300-B2
Application number	US-201916290277-A
Country	US
Kind code	B2
Filing date	Mar 1, 2019
Priority date	Mar 1, 2019
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.

First claim

What is claimed is:

1. A semiconductor structure comprising a memory die bonded to a support die, wherein:
the memory die comprises an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and comprising a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material;
the support die comprises a peripheral circuitry;
the single crystalline channel semiconductor material comprises single crystal silicon;
a crystallographic orientation of the single crystalline channel semiconductor material and a crystallographic orientation of the single crystalline substrate semiconductor material having a same Miller index are parallel to one other for each respective Miller index; and
the memory die comprises epitaxial pedestal channels comprising a respective single crystalline pillar semiconductor material in epitaxial alignment with the single crystalline substrate semiconductor material and with the single crystalline channel semiconductor material of an overlying one of the vertical semiconductor channels;
the memory die further comprises drain regions comprising a single crystalline drain semiconductor material in epitaxial alignment with the single crystalline channel semiconductor material of an underlying one of the vertical semiconductor channels;
the single crystalline channel semiconductor material and the single crystalline pillar semiconductor material include dopants of a first conductivity type at a first atomic concentration; and
the single crystalline drain semiconductor material includes dopants of a second conductivity type that is an opposite of the first conductivity type at a second atomic concentration that is greater than the first atomic concentration.

2. The semiconductor structure of claim 1 , wherein:
the memory die further comprises memory-side bonding pads formed within memory-side dielectric material layers that overlie the alternating stack and electrically connected to nodes of the memory stack structures; and
the support die further comprises support-side bonding pads formed within support-side dielectric material layers, electrically connected to nodes of the peripheral circuitry and bonded to the memory-side bonding pads.

3. The semiconductor structure of claim 1 , wherein the memory die further comprises:
a source region formed within the single crystalline substrate semiconductor material of the substrate and having a doping of the second conductivity type; and
a backside contact via structure extending through the alternating stack and contacting the source region,
wherein the single crystalline substrate semiconductor material of the substrate has a doping of the first conductivity type.

4. The semiconductor structure of claim 1 , wherein the memory die further comprises bit lines that overlie the memory stack structures and electrically connected to a respective subset of the drain regions and electrically connected to a respective one of the memory-side bonding pads.

5. The semiconductor structure of claim 1 , wherein each of the memory films laterally surrounds, and contacts, a respective one of the vertical semiconductor channels, and overlies, and contacts, a respective one of the epitaxial pedestal channels.

6. The semiconductor structure of claim 5 , wherein each of the memory films comprises:
a cylindrical portion that contacts sidewalls of the insulating layers within the alternating stack; and
an annular portion that adjoins a bottom end of the cylindrical portion, wherein one of the vertical semiconductor channels extends through an opening through the annular portion.

7. The semiconductor structure of claim 6 , wherein:
a top surface of the annular portion contacts an annular bottom surface of the one of the vertical semiconductor channels; and
a bottom surface of the annular portion contacts a top surface of an underlying one of the epitaxial pedestal channels.

8. The semiconductor structure of claim 6 , wherein an entire bottom surface of each of the drain regions contacts an entire top surface of an underlying one of the vertical semiconductor channels.

9. The semiconductor structure of claim 1 , wherein each of the memory films comprises:
a charge storage layer comprising a charge trapping material and vertically extending through the alternating stack as a continuous material layer; and
a tunneling dielectric layer contacting an inner sidewall of the charge storage layer and laterally surrounding, and contacting, a respective one of the vertical semiconductor channels.

10. The semiconductor structure of claim 1 , further comprising:
a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack to provide stepped surfaces;
a retro-stepped dielectric material portion overlying the stepped surfaces; and
contact via structures extending through the retro-stepped dielectric material portion and contacting a respective one of the electrically conductive layers.

Assignees

• Sandisk Technologies Llc

Inventors

• RAJASHEKHAR Adarsh
• Makala Raghuveer S
• Zhou Fei
• Sharangpani Rahul

Classifications

• H01L27/1157

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic