Semiconductor device and manufacturing method thereof
US-2015380425-A1 · Dec 31, 2015 · US
having at least one additional gate, e.g. program gate, erase gate or select gate
having at least one additional gate, e.g. program gate, erase gate or select gate · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D30/696 |
| Official title | {having at least one additional gate, e.g. program gate, erase gate or select gate} |
| Display label | having at least one additional gate, e.g. program gate, erase gate or select gate |
| Total patents | 1,243 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 118 |
| 2016 | 174 |
| 2017 | 157 |
| 2018 | 126 |
| 2019 | 163 |
| 2020 | 111 |
| 2021 | 107 |
| 2022 | 87 |
| 2023 | 74 |
| 2024 | 63 |
| 2025 | 53 |
| 2026 | 10 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor storage device and manufacturing method thereof
US-2015372151-A1 · Dec 24, 2015 · US
Nonvolatile semiconductor memory device and method for manufacturing same
US-2015364489-A1 · Dec 17, 2015 · US
Method of manufacturing semiconductor device and semiconductor device
US-2015333139-A1 · Nov 19, 2015 · US
Semiconductor integrated circuit device and a method of manufacturing the same
US-2015333081-A1 · Nov 19, 2015 · US
Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures
US-2015325589-A1 · Nov 12, 2015 · US
Method of Forming an Embedded Memory Device
US-2015318292-A1 · Nov 5, 2015 · US
Multi-level memory cells and methods for forming multi-level memory cells
US-9171858-B2 · Oct 27, 2015 · US
Semiconductor device and method of manufacturing semiconductor device
US-2015287832-A1 · Oct 8, 2015 · US
Semiconductor device and manufacturing method of semiconductor device
US-2015287736-A1 · Oct 8, 2015 · US
Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
US-2015287812-A1 · Oct 8, 2015 · US
Nonvolatile memory device and method for fabricating the same
US-9153704-B2 · Oct 6, 2015 · US
Semiconductor device and method of manufacturing the same
US-2015279938-A1 · Oct 1, 2015 · US
Memory Cell and Manufacturing Method Thereof
US-2015270277-A1 · Sep 24, 2015 · US
Method of forming split-gate cell for non-volative memory devices
US-2015270274-A1 · Sep 24, 2015 · US
HK embodied flash memory and methods of forming the same
US-9136393-B2 · Sep 15, 2015 · US
Method of manufacturing semiconductor device
US-2015249145-A1 · Sep 3, 2015 · US
Method for manufacturing a double-gate electronic memory cell and associated memory cell
US-9117702-B2 · Aug 25, 2015 · US
Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays
US-2015236035-A1 · Aug 20, 2015 · US
Semiconductor constructions
US-9105737-B2 · Aug 11, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D30/696?
- CPC H10D30/696 is the Cooperative Patent Classification code for “having at least one additional gate, e.g. program gate, erase gate or select gate.”
- How many patents are filed under CPC H10D30/696 (having at least one additional gate, e.g. program gate, erase gate or select gate)?
- Our database includes 1,243 publications tagged with this CPC code.
- Is patent activity under CPC H10D30/696 growing?
- Publication counts under this code: 63 in 2024 vs 53 in 2025 (latest complete years).