Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-12283577-B2
Application number	US-202217862482-A
Country	US
Kind code	B2
Filing date	Jul 12, 2022
Priority date	Dec 10, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area;
a fan-in chip structure located in the through-hole, the fan-in chip structure including a first chip, a capacitor chip arranged to be spaced apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip;
a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and
an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

2. The fan-out semiconductor package of claim 1 , wherein the package body includes a circuit board, and the circuit board includes an insulating substrate or a semiconductor substrate.

3. The fan-out semiconductor package of claim 1 , wherein the capacitor chip includes a trench capacitor or a through-via capacitor.

4. The fan-out semiconductor package of claim 1 ,
wherein a second chip pad is arranged on a bottom surface of the second chip,
wherein chip connection pads are arranged on bottom surfaces of the capacitor chip and the first chip, and
wherein the second chip pad has a different structure than the chip connection pads.

5. The fan-out semiconductor package of claim 1 ,
wherein the second chip includes a second chip pad,
wherein the first chip includes a first through-via,
wherein the capacitor chip includes a second through-via, and
wherein the second chip pad is electrically connected to the first and second through-vias.

6. The fan-out semiconductor package of claim 1 ,
wherein the first chip includes a first through-via,
wherein the capacitor chip includes a second through-via, and
wherein the redistribution structure includes a chip connection pad connected to the first and second through-vias.

7. The fan-out semiconductor package of claim 1 ,
wherein the first chip includes a first through-via and a first chip pad connected to the first through-via,
wherein the redistribution structure further includes a chip connection pad, and
wherein the first chip pad is electrically connected to the redistribution element through the chip connection pad.

8. The fan-out semiconductor package of claim 1 ,
wherein the capacitor chip includes a second through-via and a capacitor chip pad connected to the second through-via,
wherein the redistribution structure further includes a chip connection pad, and
wherein the capacitor chip pad is electrically connected to the redistribution element through the chip connection pad.

9. The fan-out semiconductor package of claim 1 ,
wherein the package body is formed as a circuit board having the through-hole located therein,
wherein the fan-in chip structure further includes a first encapsulation layer located between the first chip and the capacitor chip, and
wherein the fan-out semiconductor package further includes a second encapsulation layer sealing the fan-in chip structure embedded in the through-hole.

10. The fan-out semiconductor package of claim 1 ,
wherein the package body is formed as a circuit board having the through-hole located therein,
wherein the package body includes the body interconnect structure arranged therein, a first body interconnect pad located on a bottom surface of the package body and electrically connected to the body interconnect structure, and a second body interconnect pad located on a top surface thereof and electrically connected to the body interconnect structure,
wherein the redistribution structure is electrically connected to the first body interconnect pad in the fan-out area, and
wherein the interconnect via is electrically connected to the second body interconnect pad in the fan-out area.

11. The fan-out semiconductor package of claim 1 , wherein the package body includes an encapsulation layer that seals the fan-in chip structure located in the fan-in area and is formed in the fan-out area.

12. A fan-out semiconductor package comprising:
a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area;
a fan-in chip structure located in the through-hole, the fan-in chip structure including a first chip, a capacitor chip arranged to be spaced apart from the first chip, a first encapsulation layer located between the first chip and the capacitor chip, and a second chip having a top surface bonded to top surfaces of both the first chip and the capacitor chip;
a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the first chip and including a redistribution element extending to the fan-out area; and
an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

13. The fan-out semiconductor package of claim 12 ,
wherein the top surfaces of the first chip, the capacitor chip, and the second chip are active surfaces, and
wherein the bottom surface of the first chip and bottom surfaces of the capacitor chip and the second chip are inactive surfaces.

14. The fan-out semiconductor package of claim 12 ,
wherein the package body is a circuit board having the through-hole located therein, and
wherein the fan-out semiconductor package further comprises a second encapsulation layer formed on both sides of the fan-in chip structure within the through-hole and on the package body.

15. The fan-out semiconductor package of claim 12 , wherein the capacitor chip includes a trench capacitor or a through-via capacitor.

16. The fan-out semiconductor package of claim 12 , wherein the first chip and the capacitor chip are arranged to overlap the second chip in a planar view.

17. The fan-out semiconductor package of claim 12 ,
wherein the package body further includes a second encapsulation layer that seals the fan-in chip structure located in the fan-in area and is formed in the fan-out area, and
wherein the body interconnect structure is located in the second encapsulation layer and is electrically connected to the redistribution structure and the interconnect via.

18. A fan-out semiconductor package comprising:
a lower package; and
an upper package stacked on the lower package;
wherein the lower package comprises:
a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area;
a fan-in chip structure located in the through-hole, the fan-in chip structure including a first chip, a capacitor chip arranged to be spaced apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip;
a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area;
a first external connection terminal electrically connected to the redistribution structure on the bottom surface of the package body; and
an interconnect via and an interconnect pad arranged on a top surface

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonsung
• Lee Seokwon

Classifications

• H10W90/798

  between a chip and a stacked discrete passive device · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title