Package structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10658333-B2
Application number	US-201816199230-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Jul 31, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

First claim

What is claimed is:

1. A package structure, comprising:
at least one first semiconductor die having a semiconductor substrate and a conductive post disposed on the semiconductor substrate;
an insulating encapsulant partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant;
an isolation layer disposed on the insulating encapsulant and surrounding the second portion of the conductive post; and
a redistribution layer disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

2. The package structure according to claim 1 , wherein the isolation layer separates the redistribution layer from the insulating encapsulant.

3. The package structure according to claim 1 , wherein the first semiconductor die further comprises a protection layer disposed on the semiconductor substrate and surrounding the conductive post, the isolation layer surrounds the protection layer, and a top surface of the protection layer is coplanar with a top surface of the isolation layer.

4. The package structure according to claim 1 , wherein the semiconductor die further comprises a protection layer disposed on the semiconductor substrate and surrounding the conductive post, the isolation layer surrounds the protection layer, and a top surface of the protection layer is lower than a top surface of the isolation layer.

5. The package structure according to claim 1 , wherein the isolation layer surrounds and is in contact with the conductive post.

6. The package structure according to claim 1 , further comprising a plurality of through insulator vias surrounding the semiconductor die, wherein the plurality of through insulator vias protrude out from the insulating encapsulant and the isolation layer surrounds the protruded portion of the plurality of through insulator vias.

7. The package structure according to claim 1 , further comprising a second semiconductor die stacked on the first semiconductor die, the second semiconductor die comprises a second semiconductor substrate and a second conductive post disposed on the second semiconductor substrate, wherein the second conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant, and the isolation layer surrounds the second portion of the second conductive post.

8. The package structure according to claim 7 , wherein a top surface of the conductive post of the first semiconductor die is substantially coplanar with a top surface of the second conductive post of the second semiconductor die.

9. A package structure, comprising:
a first semiconductor die having a semiconductor substrate and a plurality of conductive posts disposed on the semiconductor substrate;
an insulating encapsulant partially encapsulating the first semiconductor die, wherein a top surface of the insulating encapsulant is lower than a level of a top surface of the plurality of conductive posts;
an isolation layer disposed on the top surface of the insulating encapsulant and surrounding the plurality of conductive posts, wherein a top surface of the isolation layer is substantially coplanar with the top surface of the plurality of conductive posts, and a ratio of a thickness of the isolation layer to a thickness of the insulating encapsulant is in a range of 1:6 to 1:40; and
a redistribution layer disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the plurality of conductive posts of the first semiconductor die.

10. The package structure according to claim 9 , wherein the isolation layer separates the redistribution layer from the insulating encapsulant.

11. The package structure according to claim 9 , wherein the first semiconductor die further comprises a protection layer disposed on the semiconductor substrate and surrounding the plurality of conductive posts, the isolation layer surrounds the protection layer, and a top surface of the protection layer is coplanar with the top surface of the isolation layer.

12. The package structure according to claim 9 , wherein the isolation layer surrounds and is in contact with each of the plurality of conductive posts.

13. The package structure according to claim 9 , wherein a portion of the plurality of conductive posts is surrounded by the insulating encapsulant, and another portion of the plurality of conductive posts is surrounded by the isolation layer.

14. The package structure according to claim 9 , further comprising a second semiconductor die stacked on the first semiconductor die, the second semiconductor die comprises a second semiconductor substrate and a plurality of second conductive posts disposed on the second semiconductor substrate, wherein the insulating encapsulant partially encapsulates the second semiconductor die, and the top surface of the isolation layer is coplanar with a top surface of the plurality of second conductive posts.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chen Ming-Fa
• Yeh Sung-Feng

Classifications

• H01L24/17

  Electricity · mapped topic

• H01L24/73

  Electricity · mapped topic

• H01L23/3128

  Electricity · mapped topic

• H01L24/30

  Electricity · mapped topic

• H01L2224/0231

  Electricity · mapped topic