Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9620482-B1
Application number	US-201514886560-A
Country	US
Kind code	B1
Filing date	Oct 19, 2015
Priority date	Oct 19, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric. In the semiconductor device, a height of the conductive post is greater than the vertical height.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of semiconductor dies stacked vertically to have a vertical height;
a dielectric surrounding the stacked semiconductor dies; and
a conductive post external to the stacked semiconductor dies and extending through the dielectric; wherein
a height of the conductive post is greater than the vertical height, the plurality of semiconductor dies includes a first component and a second component, and the first component is stacked vertically on the second component, and a width of the first component is less than a width of the second component.

2. The semiconductor device of claim 1 , wherein the height of the conductive post is greater than about 250 um.

3. The semiconductor device of claim 1 , wherein a width of the conductive post is less than about 285 um.

4. The semiconductor device of claim 1 , wherein a difference between the width of the first component and the width of the second component is greater than about 100 um.

5. The semiconductor device of claim 1 , further comprising a third component, wherein the third component is stacked vertically on the second component and adjacent to the first component.

6. The semiconductor device of claim 5 , wherein a width of the second component is greater than a sum of a width of the first component and a width of the third component.

7. The semiconductor device of claim 1 , wherein further comprises a thermal dissipation pad electrically connected to the plurality of semiconductor dies and configured to dissipate a heat from the plurality of semiconductor dies.

8. The semiconductor device of claim 1 , wherein the conductive post is configured as a support for the plurality of semiconductor dies.

9. The semiconductor device of claim 1 , further comprising a plurality of conductive posts, wherein the plurality of the conductive posts surrounds the plurality of semiconductor dies.

10. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
disposing a conductive post over the substrate, wherein a height of the conductive post is more than about 250 um;
stacking a plurality of semiconductor dies vertically over the substrate and adjacent to the conductive post;
disposing a dielectric to surround the conductive post and the plurality of semiconductor dies; and
electrically connecting the plurality of semiconductor dies through the conductive post.

11. The method of claim 10 , wherein stacking the plurality of semiconductor dies comprises stacking a first semiconductor die vertically on a second semiconductor die.

12. The method of claim 11 , wherein a width of the second semiconductor die is substantial greater than a width of the first semiconductor die.

13. The method of claim 11 , wherein a difference of the width of the second semiconductor die and the width of the first semiconductor die is greater than 100 um.

14. A method of manufacturing a semiconductor device, comprising:
stacking a plurality of semiconductor dies vertically;
providing a substrate;
disposing a conductive post over the substrate, wherein a height of the conductive post is more than about 250 um;
placing the plurality of semiconductor dies adjacent to the conductive post; and
disposing a dielectric to surround the conductive post and the plurality of semiconductor dies; and
electrically connecting the plurality of semiconductor dies through the conductive post.

15. The method of claim 14 , wherein stacking the plurality of semiconductor dies comprises singulating a wafer level package into the plurality of semiconductor dies.

16. The method of claim 14 , further comprising removing a portion of the dielectric to expose a top surface of the conductive post and a top surface of the plurality of semiconductor dies.

17. The method of claim 16 , wherein removing a portion of the dielectric is performed by etching or grinding.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yu-Jen
• Chen Hsien-Wei
• Yeh Der-Chyang

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title