Devices, packaged semiconductor devices, and semiconductor device packaging methods

Patent metadata

Field	Value
Publication number	US-9773757-B2
Application number	US-201615145551-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	Jan 19, 2016
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first interconnect structure, a first integrated circuit die coupled to the first interconnect structure, and a second integrated circuit die disposed over and coupled to the first integrated circuit die. A second interconnect structure is disposed over the second integrated circuit die. First through-vias are coupled between the first interconnect structure and the second interconnect structure, and second through-vias are coupled between the first integrated circuit die and the second interconnect structure. A molding material is disposed around the first integrated circuit die, the second integrated circuit die, the plurality of first through-vias, and the plurality of second through-vias.

First claim

What is claimed is:

1. A device comprising:
a first interconnect structure;
a plurality of first integrated circuit dies coupled to the first interconnect structure;
an adhesive layer over each of the first integrated circuit dies;
a second integrated circuit die disposed over and adhered to each of the first integrated circuit dies with the adhesive layer;
a second interconnect structure disposed over the second integrated circuit die;
a plurality of first through-vias coupled between the first interconnect structure and the second interconnect structure;
a plurality of second through-vias coupled between the first integrated circuit dies and the second interconnect structure; and
a molding material disposed around the first integrated circuit dies, the second integrated circuit die, the adhesive layer, the plurality of first through-vias, and the plurality of second through-vias.

2. The device according to claim 1 , wherein each of the plurality of first integrated circuit dies is coupled to the first interconnect structure.

3. The device according to claim 1 , further comprising a third integrated circuit die coupled between the plurality of first integrated circuit dies and the second integrated circuit die, and further comprising a plurality of third through-vias coupled between the third integrated circuit die and the second interconnect structure, the plurality of third through-vias being disposed within the molding material.

4. The device according to claim 3 , further comprising a plurality of the third integrated circuit dies coupled between the plurality of first integrated circuit dies and the second integrated circuit die, wherein each of the plurality of third integrated circuit dies comprises a plurality of third through-vias coupled between the third integrated circuit die and the second interconnect structure.

5. The device according to claim 1 , further comprising a plurality of the second integrated circuit dies, wherein each of the plurality of second integrated circuit dies is coupled to the first integrated circuit die.

6. The device according to claim 1 , wherein the second integrated circuit die has contact pads, and the second interconnect structure is coupled to the contact pads of the second integrated circuit die by conductive pillars.

7. A packaged semiconductor device comprising:
a first interconnect structure having first conductive features disposed thereon;
a plurality of first integrated circuit dies coupled to the first interconnect structure, the first integrated circuit dies having first contact pads disposed thereon;
a second integrated circuit die disposed over and adhered to each of the first integrated circuit dies with an adhesive layer, the second integrated circuit die having second contact pads disposed thereon;
a second interconnect structure disposed over the second integrated circuit die, the second interconnect structure having second conductive features, third conductive features, and fourth conductive features disposed thereon, the second conductive features of the second interconnect structure being coupled to the second contact pads of the second integrated circuit die;
a plurality of first through-vias coupled between the first conductive features of the first interconnect structure and the third conductive features of the second interconnect structure;
a plurality of second through-vias coupled between the first contact pads of the first integrated circuit dies and the fourth conductive features of the second interconnect structure; and
a molding material disposed around the first integrated circuit dies, the second integrated circuit die, the adhesive layer, the plurality of first through-vias, and the plurality of second through-vias.

8. The packaged semiconductor device according to claim 7 , wherein the second conductive features of the second interconnect structure are coupled to the second contact pads of the second integrated circuit die by conductive pillars.

9. The packaged semiconductor device according to claim 7 , wherein the second conductive features, third conductive features, and fourth conductive features of the second interconnect structure are disposed on a first side of the second interconnect structure, and further comprising a third integrated circuit die or a passive component coupled to a second side of the second interconnect structure, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.

10. The packaged semiconductor device according to claim 7 , wherein the second conductive features, third conductive features, and fourth conductive features of the second interconnect structure are disposed on a first side of the second interconnect structure, and further comprising a plurality of connectors coupled to a second side of the second interconnect structure, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.

11. The packaged semiconductor device according to claim 10 , wherein the packaged semiconductor device comprises a first packaged semiconductor device, further comprising a second packaged semiconductor device coupled to the plurality of connectors.

12. The packaged semiconductor device according to claim 7 , wherein the first conductive features of the first interconnect structure are disposed on a first side of the first interconnect structure, and further comprising a plurality of connectors coupled to a second side of the first interconnect structure, the second side of the first interconnect structure being opposite the first side of the first interconnect structure.

13. A method of packaging semiconductor devices, the method comprising:
forming a first interconnect structure over a carrier;
coupling a plurality of first through-vias to the first interconnect structure;
coupling a first integrated circuit die to the first interconnect structure;
coupling a plurality of second through-vias to the first integrated circuit die;
coupling a second integrated circuit die to the first integrated circuit die;
forming a molding material over the first interconnect structure and around the plurality of first through-vias, the first integrated circuit die, the plurality of second through-vias, and the second integrated circuit die;
forming a second interconnect structure over the molding material, the plurality of first through-vias, the plurality of second through-vias, and the second integrated circuit die; and
after the forming the second interconnect structure, removing the carrier.

14. The method according to claim 13 , wherein forming the first interconnect structure or forming the second interconnect structure comprises forming a redistribution layer (RDL) comprising fan-out wiring.

15. The method according to claim 13 , wherein the method further comprises singulating the second interconnect structure, the molding material, and the first interconnect structure to form a plurality of packaged semiconductor devices.

16. The method according to claim 13 , wherein coupling a second integrated circuit die to the first integrated circuit die comprises coupling a plurality of the second integrated circuit dies to the first integrated circuit die, and wherein coupling the plurality of second integrated circuit dies comprises coupling a vertical stack of the plurality of second integrated circuit dies.

17. The method according to claim 13 , wherein coupling the second integrated circuit die to the first integrated circuit die comprises extending a p

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yee Kuo-Chung

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title