Semiconductor device

Patent metadata

Field	Value
Publication number	US-12279421-B2
Application number	US-202318190253-A
Country	US
Kind code	B2
Filing date	Mar 27, 2023
Priority date	Jun 8, 2020
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first substrate including a first portion and a second portion spaced apart from the first portion, the first portion being a first polysilicon plate portion and the second portion being a second polysilicon plate portion;
a lower separation region including an insulating material between the first portion and the second portion;
a first stack structure on the first portion;
a second stack structure on the second portion and spaced apart from the first stack structure;
an intermediate stack structure between the first stack structure and the second stack structure, and spaced apart from the first and second stack structures;
first block separation structures penetrating through the first stack structure;
second block separation structures penetrating through the second stack structure; and
a contact plug penetrating through the intermediate stack structure,
wherein each of the first and second stack structures includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction,
wherein the intermediate stack structure includes first layers and second layers alternately stacked in the vertical direction,
wherein each of the first and second block separation structures extends in a first direction parallel to an upper surface of the first substrate,
wherein the contact plug does not vertically overlap with the first and second portions and is spaced apart from the first and second portions,
wherein lower surfaces of the first and second block separation structures are at a higher level than lower surfaces of the first and second portions where the first and second block separation structures contact the first and second portions, respectively,
wherein a material of the first layers is the same material as a material of the interlayer insulating layers, and
wherein an uppermost gate electrode of the gate electrodes is at a same level as an uppermost second layer of the second layers.

2. The semiconductor device of claim 1 , further comprising:
a first intermediate separation structure between the contact plug and the first stack structure; and
a second intermediate separation structure between the contact plug and the second stack structure, wherein
the uppermost gate electrode of the first stack structure contacts the first intermediate separation structure, and
wherein the uppermost gate electrode of the second stack structure contacts the second intermediate separation structure.

3. The semiconductor device of claim 1 , further comprising:
a first intermediate separation structure between the contact plug and the first stack structure; and
a second intermediate separation structure between the intermediate stack structure and the second stack structure,
wherein the second layers include a material different from a material of the gate electrodes.

4. The semiconductor device of claim 3 , wherein the contact plug penetrates through the first layers and the second layers of the intermediate stack structure.

5. The semiconductor device of claim 4 , further comprising:
first channel structures penetrating through the first stack structure; and
second channel structures penetrating through the second stack structure,
wherein an upper surface of the contact plug is at a higher level than upper surfaces of the first and second channel structures,
wherein the first channel structures are connected to the first portion, and
wherein the second channel structures are connected to the second portion.

6. The semiconductor device of claim 1 , wherein
the first substrate further includes a third portion between the first portion and the second portion,
the third portion is spaced apart from the first and second portions,
the third portion includes a polysilicon layer, and
the third portion is vertically overlapped by the intermediate stack structure.

7. The semiconductor device of claim 2 , wherein
the first substrate further includes a third portion between the first portion and the second portion,
the third portion is spaced apart from the first and second portions,
the third portion includes a polysilicon layer, and
the third portion is vertically overlapped by the intermediate stack structure.

8. The semiconductor device of claim 4 ,
wherein the first substrate further includes a third portion between the first portion and the second portion,
wherein the third portion is spaced apart from the first portion and the second portion, and
the contact plug is connected to the third portion.

9. The semiconductor device of claim 1 , further comprising:
a peripheral circuit region vertically overlapped by the first stack structure, the second stack structure, and the intermediate stack structure.

10. The semiconductor device of claim 9 ,
wherein the peripheral circuit region includes a base substrate and a circuit device including a transistor.

11. A semiconductor device, comprising:
a peripheral circuit region; and
a memory cell region vertically overlapping the peripheral circuit region,
wherein the memory cell region includes,
a first substrate including a first portion and a second portion spaced apart from the first portion,
first stack structures on the first portion,
second stack structures on the second portion and spaced apart from the first stack structure, and
an intermediate stack structure between the first stack structure and the second stack structure, and spaced apart from the first and second stack structures,
first channel structures penetrating through the first stack structures,
second channel structures penetrating through the second stack structures, and
a contact plug penetrating through the intermediate stack structure, wherein each of the first and second portions include a polysilicon layer,
the contact plug does not vertically overlap with the first and second portions and is spaced apart from the first and second portions,
each of the first and second stack structures includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction,
the intermediate stack structure includes first layers and second layers alternately stacked in the vertical direction,
the contact plug penetrates through the first layers and the second layers of the intermediate stack structure,
a lower end of each of the first and second channel structures is at a higher level than lower surfaces of the first and second portions,
a material of the first layers is the same material as a material of the interlayer insulating layers,
an uppermost gate electrode of the gate electrodes is at a same level as an uppermost second layer of the second layers,
the first substrate further includes a third portion between the first portion and the second portion,
the third portion is spaced apart from the first and second portions,
the intermediate stack structure vertically overlaps the third portion, and
each of the first, second and third portions includes a polysilicon layer.

12. The semiconductor device of claim 11 ,
wherein each of the first and second stack structures extends in a first horizontal direction,
wherein the first stack structures are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction,
wherein the second stack structures are spaced apart from each other in the second horizontal direction, and
wherein the intermediate stack structure extends in the horizontal second direction.

13. The semiconductor device of claim 11 ,
wherein the intermediate stack structure includes:
a first inter

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Sangyoun
• Kanamori Kohji
• Jung Kwangyoung
• Han Jeehoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title