Wiring line structure of three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10388663-B2
Application number	US-201815878806-A
Country	US
Kind code	B2
Filing date	Jan 24, 2018
Priority date	Aug 22, 2017
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate;
a plurality of gate lines stacked over the substrate along the first direction, the gate lines surrounding the channel structures, wherein the gate lines extend in a second direction that is parallel to the top surface of the substrate;
at least one wiring line formed at a respective layer of at least one of the gate lines by separating the at least one wiring line from the respective layer of the at least one of the gate lines with a cutting pattern, wherein the at least one wiring line extends in the second direction;
a block decoder disposed at one side of the gate lines and the at least one wiring line in the second direction; and
a pass transistor disposed at the other side of the gate lines and the at least one wiring line in the second direction, coupled to one of the gate lines and electrically coupled to the block decoder through the at least one wiring line, and transferring an operation voltage to the gate line in response to a block select signal provided from the block decoder.

2. The memory device according to claim 1 ,
wherein the gate lines include at least one source select line, a plurality of word lines and at least one drain select line which are sequentially stacked along the first direction, and
wherein one of the at least one wiring line is formed at a layer of the drain select line.

3. The memory device according to claim 2 , wherein the at least one wiring line overlaps with the source select line and the word lines in the first direction.

4. The memory device according to claim 1 ,
wherein the gate lines include at least one source select line, a plurality of word lines and at least one drain select line which are sequentially stacked along the first direction, and
wherein the at least one wiring line is formed at each layer of the source select line, the word lines and the drain select line, respectively.

5. The memory device according to claim 1 , wherein the cutting pattern is formed of a dielectric material.

6. A memory device comprising:
a substrate;
channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate;
a plurality of gate lines stacked over the substrate along the first direction, the gate lines surrounding the channel structures, wherein the gate lines extend in a second direction that is parallel to the top surface of the substrate;
at least one wiring line formed at a respective layer of at least one of the gate lines by separating the at least one wiring line from the respective layer of the at least one of the gate lines with a cutting pattern, wherein the at least one wiring line extends in the second direction;
a global line controller disposed at one side of the gate lines and the at least one wiring line in the second direction; and
a pass transistor disposed at the other side of the gate lines and the at least one wiring line in the second direction, coupled to one of the gate lines and electrically coupled to the global line controller through the at least one wiring line, and transferring an operation voltage provided from the global line controller to the gate line.

7. A memory device comprising:
a substrate;
a memory block stacked over the substrate in a first direction perpendicular to a top surface of the substrate,
the memory block comprising:
channel structures extending in the first direction;
at least one source select line, a plurality of word lines and at least one drain select line surrounding the channel structures and stacked along the first direction, wherein the at least one source select line, the plurality of word lines and the at least one drain select line extend in a second direction that is parallel to the top surface of the substrate; and
a wiring line formed at a layer of the drain select line by separating the wiring line from the layer of the drain select line with a cutting pattern, wherein the wiring line extends in the second direction,

a block decoder disposed at one side of the memory block in the second direction; and
a pass transistor disposed at the other side of the memory block in the second direction, coupled to one of the at least one source select line, the plurality of word lines and the at least one drain select line and electrically coupled to the block decoder through the wiring line, and transferring an operation voltage to the one of the at least one source select line, the plurality of word lines and the at least one drain select line in response to a block select signal provided from the block decoder.

8. A memory device comprising:
a substrate;
a memory cell array stacked over the substrate in a first direction perpendicular to a top surface of the substrate,
the memory cell array comprising:
a memory block including channel structures which extend in the first direction and a plurality of gate lines which surround the channel structures and are stacked over the substrate along the first direction, wherein the gate lines extend in a second direction that is parallel to the top surface of the substrate; and
a wiring line stack including a plurality of wiring lines which are stacked over the substrate along the first direction, wherein each of the plurality of wiring lines is formed at a layer of a respective gate line, wherein the wiring lines extend in the second direction,

a block decoder disposed at one side of the memory cell array in the second direction; and
a pass transistor disposed at the other side of the memory cell array in the second direction, coupled to one of the gate lines and electrically coupled to the block decoder through one of the wiring lines, and transferring an operation voltage to the gate line in response to a block select signal provided from the block decoder.

9. The memory device according to claim 8 , further comprising:
a well region formed in the substrate, and overlapping with the memory block in the first direction; and
an isolation structure formed in the substrate, overlapping with the wiring line stack in the first direction, and electrically decoupled from the well region.

10. The memory device according to claim 8 , further comprising:
supports passing through the wiring line stack in the first direction.

11. The memory device according to claim 10 , wherein the supports have the same structure as the channel structures.

12. The memory device according to claim 10 , further comprising:
an interlayer dielectric layer formed over the substrate to cover the memory cell array;
a plurality of bit lines formed over the interlayer dielectric layer; and
bit line contacts disposed over the channel structures, respectively, and electrically coupling the channel structures to the bit lines through the interlayer dielectric layer,
wherein the supports are electrically decoupled from the bit lines by the interlayer dielectric layer.

13. A memory device comprising:
a substrate;
a memory cell array stacked over the substrate in a first direction perpendicular to a top surface of the substrate,
the memory cell array comprising:
a memory block including channel structures which extend in the first direction and a plurality of gate lines which surround the channel structures and are stacked over the substrate along the first direction, wherein the gate lines extend in a second direction that is parallel to the top surface of the substrate; and
a wiring line stack including a plurality of wiring lines which are stacked ov

Assignees

• Sk Hynix Inc

Inventors

• Oh Sung-Lae
• Kim Dong-Hyuk
• Jung Soo-Nam

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title