Memory structure

Patent metadata

Field	Value
Publication number	US-9812176-B2
Application number	US-201615364291-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Aug 25, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1.

First claim

What is claimed is:

1. A memory structure, comprising:
N array regions, wherein N is an integer≧2, and each of the N array regions comprises:
a 3D array of a plurality of memory cells, wherein the memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array; and
a plurality of conductive lines disposed over and coupled to the 3D array, wherein the conductive lines have a pitch p, and p/d=⅕ to ½; and
N page buffers coupled to the N array regions, respectively;
wherein the N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines; and
wherein M array regions of the N array regions are configured to operate simultaneously, M is an integer, and M/N=1.

2. The memory structure according to claim 1 , wherein p/d=⅕, ¼, ⅓, or ½.

3. The memory structure according to claim 1 , wherein p is 38 nm to 120 nm.

4. The memory structure according to claim 1 , further comprising:
at least N decoders, wherein each of the at least N decoders is disposed adjacent to corresponding one of the N array regions in a direction perpendicular to the extension direction of the conductive lines and coupled to the corresponding one of the N array regions.

5. The memory structure according to claim 4 , wherein a number of the at least N decoders is 2N, and every two of the 2N decoders are disposed on two sides of the corresponding one of the N array regions in the direction perpendicular to the extension direction of the conductive lines.

6. The memory structure according to claim 1 , wherein N is an even number, and wherein the N array regions comprise a (2n−1) th array region and a 2n th array region, and n is an integer from 1 to N/2.

7. The memory structure according to claim 6 , wherein the (2n−1) th array region and the 2n th array region are spatially separated from each other by two of the N page buffers, which are coupled to the (2n−1) th array region and the 2n th array region, respectively.

8. The memory structure according to claim 6 , wherein the (2n−1) th array region and the 2n th array region are disposed substantially in a mirror way.

9. The memory structure according to claim 6 , wherein the conductive lines of the (2n−1) th array region and the conductive lines of the 2n th array region are misaligned.

10. The memory structure according to claim 1 , wherein the conductive lines are bit lines.

11. The memory structure according to claim 1 , wherein each of the M array regions comprises a plurality of blocks, and each of the blocks corresponds to a common gate of a plurality of word line drivers for a plurality of word lines of the each of the blocks; and
wherein a set of M blocks, which belong to the M array regions, respectively, are coupled by a connection of the common gates of the set of M blocks.

12. The memory structure according to claim 1 , wherein each of the M array regions comprises a plurality of blocks, and each of the blocks corresponds to a common gate of a plurality of word line drivers for a plurality of word lines of the each of the blocks; and
wherein a set of M blocks, which belong to the M array regions, respectively, are coupled by a connection of control gates of the common gates of the set of M blocks.

13. The memory structure according to claim 1 , comprising N planes,
wherein the N planes comprises the N array regions, respectively, and
wherein a word line address is separated into M planes of the N planes.

14. A memory structure, comprising:
array regions each comprising a 3D array of a plurality of memory cells, wherein each of the array regions comprises blocks, each of the blocks comprises a plurality of word lines;
a plurality of word line drivers having first transistors, wherein the first transistors have common gates; and
second transistors having control gates, wherein a set of the blocks belonging to the array regions respectively are coupled by a series connection of electrodes of the common gates corresponding to the set of the blocks to sources/drains of the second transistors.

15. The memory structure according to claim 14 , wherein the blocks of the array regions are arranged in a mirror way.

16. The memory structure according to claim 14 , wherein the array regions comprise a first array region comprising the blocks comprising a first block, a second block, a third block and a fourth block in sequence, the plurality of the word line drivers corresponding to the first block and the third block is in a region on the same side of the first array region.

17. The memory structure according to claim 14 , wherein the array regions comprise a first array region and a second array region, the each of the blocks comprises a first block and a second block,
the set of the blocks are the first blocks of the first array region and the second array region, or the second blocks of the first array region and the second array region.

18. The memory structure according to claim 17 , wherein the plurality of the word line drivers corresponding to the first block and the second block of the first array region are disposed in regions on opposing sides of the first array region respectively.

19. The memory structure according to claim 14 , wherein the plurality of word line drivers corresponding the plurality of word lines of one of the blocks are in a region on the same side of the corresponding one of the array region.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Shih-Hung

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C8/10

  Decoders · CPC title