Methods for forming three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-2020027892-A1
Application number	US-201816137638-A
Country	US
Kind code	A1
Filing date	Sep 21, 2018
Priority date	Jul 20, 2018
Publication date	Jan 23, 2020
Grant date	—

Abstract

Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.

First claim

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral device on a first substrate; forming, on the first substrate, a first interconnect layer above the peripheral device; forming, on a second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack; forming, on the second substrate, a second interconnect layer above the memory strings; bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer; forming a staircase structure at an edge of the dielectric stack; thinning the second substrate after the bonding; and forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs, wherein forming the staircase structure comprises prior to forming the memory stack, performing a plurality of trim-etch cycles for the dielectric/sacrificial layer pairs toward the first substrate.

2 - 3 . (canceled)

4 . The method of claim 1 , further comprising forming a plurality of first via contacts such that each of the first via contacts is above and in contact with a conductor layer of one of the conductor/dielectric layer pairs.

5 . The method of claim 1 , further comprising forming a plurality of second via contacts such that each of the second via contacts is above and in contact with one of the memory strings.

6 . The method of claim 1 , further comprising forming a third interconnect layer above the thinned second substrate after forming the memory stack.

7 . The method of claim 1 , wherein the bonding includes hybrid bonding.

8 . (canceled)

9 . The method of claim 1 , wherein bonding the first substrate and the second substrate comprises flipping the second substrate upside down.

10 - 13 . (canceled)

14 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral device on a first substrate; forming, on the first substrate, a first interconnect layer above the peripheral device; forming a plurality of memory strings each extending vertically on a second substrate; forming, on the second substrate, a second interconnect layer above the memory strings; forming, on the second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs through which the memory strings extend vertically, bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer; thinning the second substrate after the bonding; and forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs, wherein edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the first substrate are staggered laterally toward the memory strings, wherein forming the memory stack comprises forming the staircase structure at an edge of the dielectric stack and replacing sacrificial layers in the dielectric/sacrificial layer pairs by a plurality of conductor layers, and forming the staircase structure comprises performing a plurality of trim-etch cycles for the dielectric/sacrificial layer pairs toward the first substrate.

15 . The method of claim 14 , further comprising forming a plurality of first via contacts such that each of the first via contacts is above and in contact with a conductor layer of one of the conductor/dielectric layer pairs.

16 . The method of claim 14 , further comprising forming a plurality of second via contacts such that each of the second via contacts is above and in contact with one of the memory strings.

17 . The method of claim 14 , further comprising forming a third interconnect layer above the thinned second substrate after forming the memory stack.

18 . The method of claim 14 , wherein the bonding includes hybrid bonding.

19 . The method of claim 14 , wherein bonding the first substrate and the second substrate comprises flipping the second substrate upside down.

20 . (canceled)

21 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral device on a first substrate; forming, on the first substrate, a first interconnect layer above the peripheral device; forming, on a second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack; forming, on the second substrate, a second interconnect layer above the memory strings; bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer; thinning the second substrate after the bonding; and forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs, wherein forming the memory stack comprises etching an opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs, etching the sacrificial layers in the plurality of dielectric/sacrificial layer pairs through the opening, and depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the opening.

22 . The method of claim 21 , further comprising after the bonding, forming a staircase structure at an edge of the dielectric stack.

23 . The method of claim 22 , wherein forming the staircase structure comprises prior to forming the memory stack, performing a plurality of trim-etch cycles for the dielectric/sacrificial layer pairs toward the first substrate.

24 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral device on a first substrate; forming, on the first substrate, a first interconnect layer above the peripheral device; forming a plurality of memory strings each extending vertically on a second substrate; forming, on the second substrate, a second interconnect layer above the memory strings; forming, on the second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs through which the memory strings extend vertically, bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer; thinning the second substrate after the bonding; and forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs, wherein edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the first substrate are staggered laterally toward the memory strings, wherein forming the memory stack comprises forming the staircase structure at an edge of the dielectric stack and replacing sacrificial layers in the dielectric/sacrificial layer pairs by a plurality of conductor layers, and replacing the sacrificial layers comprises etching an opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs, etching the sacrificial

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhu Jifeng
• Chen Jun
• Lu Zhenyu
• Tao Qian
• Hu Si Ping
• Wang jia wen
• Fu Yang

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L21/76802

  Electricity · mapped topic

• H01L27/11573 Primary

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic