Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12243945-B2
Application number	US-202418619261-A
Country	US
Kind code	B2
Filing date	Mar 28, 2024
Priority date	Jul 6, 2018
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M. The third oxide and the fourth oxide include a region where the concentration of the element M is higher than that in the second oxide.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first insulator;
a second insulator over the first insulator;
a first oxide over the second insulator;
a second oxide and a third oxide over the first oxide; and
a first conductor over the second oxide;
a second conductor over the third oxide;
a fourth oxide over the first oxide;
a third insulator over the fourth oxide;
a third conductor over the third insulator; and
a fourth insulator over the first conductor and the second conductor,
wherein the fourth oxide is in contact with a top surface of the first oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the second oxide, and a side surface of the third oxide,
wherein the fourth oxide is in contact with a side surface of an opening portion provided in the fourth insulator,
wherein the third conductor is provided in the opening portion,
wherein the second insulator comprises silicon and oxygen,
wherein the first oxide comprises indium and oxygen,
wherein the second oxide and the third oxide each comprise indium, gallium, and zinc,
wherein the third insulator comprises a first insulating layer and a second insulating layer over the first insulating layer,
wherein the fourth oxide comprises aluminum,
wherein the first insulating layer comprises silicon oxide, and
wherein the second insulating layer comprises hafnium oxide.

2. The semiconductor device according to claim 1 ,
wherein the second oxide and the third oxide each comprise a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm.

3. The semiconductor device according to claim 1 ,
wherein the second oxide and the third oxide each comprise a region having a thickness of greater than or equal to 1 nm and less than or equal to 3 nm.

4. The semiconductor device according to claim 1 ,
wherein the second oxide and the third oxide each have crystallinity.

5. The semiconductor device according to claim 1 ,
wherein the first oxide has crystallinity.

6. A semiconductor device comprising:
a first insulator;
a second insulator over the first insulator;
a first oxide over the second insulator;
a second oxide and a third oxide over the first oxide; and
a first conductor over the second oxide;
a second conductor over the third oxide;
a fourth oxide over the first oxide;
a third insulator over the fourth oxide;
a third conductor over the third insulator; and
a fourth insulator over the first conductor and the second conductor,
wherein the fourth oxide is in contact with a top surface of the first oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the second oxide, and a side surface of the third oxide,
wherein the fourth oxide is in contact with a side surface of an opening portion provided in the fourth insulator,
wherein the third conductor is provided in the opening portion,
wherein the second insulator comprises silicon, nitrogen and oxygen,
wherein the first oxide comprises indium and oxygen,
wherein the second oxide and the third oxide each comprise indium, gallium, and zinc,
wherein the third insulator comprises a first insulating layer and a second insulating layer over the first insulating layer,
wherein the fourth oxide comprises aluminum,
wherein the first insulating layer comprises silicon oxide, and
wherein the second insulating layer comprises hafnium oxide.

7. The semiconductor device according to claim 6 ,
wherein the second oxide and the third oxide each comprise a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm.

8. The semiconductor device according to claim 6 ,
wherein the second oxide and the third oxide each comprise a region having a thickness of greater than or equal to 1 nm and less than or equal to 3 nm.

9. The semiconductor device according to claim 6 ,
wherein the second oxide and the third oxide each have crystallinity.

10. The semiconductor device according to claim 6 ,
wherein the first oxide has crystallinity.

11. The semiconductor device according to claim 6 ,
wherein plasma treatment is performed on the second insulator.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Baba Haruyuki
• Okuno Naoki
• Komatsu Yoshihiro
• Ohno Toshikazu

Classifications

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title