Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9935203-B2
Application number	US-201715696231-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Aug 26, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an oxide semiconductor;
a first conductor;
a second conductor;
a third conductor;
a fourth conductor;
a fifth conductor;
a first insulator;
a second insulator; and
a third insulator,
wherein the second insulator is provided with an opening portion penetrating through the second insulator,
wherein a region of a bottom surface of the opening portion is in contact with the oxide semiconductor,
wherein a region of the first insulator is in contact with a side surface and the bottom surface of the opening portion,
wherein a region of the first conductor faces the side surface and the bottom surface of the opening portion with the first insulator positioned therebetween,
wherein the second conductor, the third conductor, the fourth conductor, and the fifth conductor are positioned between the oxide semiconductor and the second insulator,
wherein a region of a side surface of the second conductor and a bottom surface of the second conductor is in contact with the fourth conductor,
wherein a region of a side surface of the third conductor and a bottom surface of the third conductor is in contact with the fifth conductor, and
wherein a region of the third insulator is in contact with the oxide semiconductor.

2. The semiconductor device according to claim 1 , wherein the third insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen.

3. The semiconductor device according to claim 1 ,
wherein a region of a fourth insulator is in contact with the first insulator, and
wherein the fourth insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen.

4. The semiconductor device according to claim 1 , wherein the first conductor comprises a region functioning as a gate electrode of a transistor having a gate line width longer than or equal to 3 nm and shorter than or equal to 60 nm.

5. The semiconductor device according to claim 1 , further comprising a region in which a distance between an end portion of the second conductor and an end portion of the third conductor facing the second conductor is longer than or equal to 5 nm and shorter than or equal to 80 nm.

Assignees

• Semiconductor Energy Lab

Inventors

• Sasagawa Shinya
• Hamada Takashi
• Shimomura Akihisa
• Okamoto Satoru
• Tochibayashi Katsuaki

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title