Semiconductor device and manufacturing method thereof

US9773919B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9773919-B2
Application numberUS-201615235242-A
CountryUS
Kind codeB2
Filing dateAug 12, 2016
Priority dateAug 26, 2015
Publication dateSep 26, 2017
Grant dateSep 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulator over a first insulator; forming an oxide semiconductor over the second insulator; forming a third insulator over the oxide semiconductor; forming a resist mask over the third insulator by a lithography method; etching part of the third insulator using the resist mask as an etching mask to form, in the third insulator, an opening portion for exposing a top surface of the oxide semiconductor; forming a first conductor over the third insulator and the exposed top surface of the oxide semiconductor; forming a second conductor over the first conductor; polishing the second conductor and the first conductor to expose the third insulator; etching the exposed portion of the third insulator; etching the oxide semiconductor and the second insulator using the first conductor and the second conductor as an etching mask until the first insulator is exposed; forming a fourth insulator over the first insulator, the first conductor, and the second conductor; forming, in the fourth insulator, an opening portion for exposing the second conductor; forming, in the second conductor, an opening portion for exposing the first conductor to divide the second conductor into a first conductor layer and a second conductor layer; forming, in the first conductor, an opening portion for exposing the oxide semiconductor to divide the first conductor into a third conductor layer and a fourth conductor layer; forming a fifth insulator over the fourth insulator and the oxide semiconductor; forming a third conductor over the fifth insulator; and polishing the third conductor and the fifth insulator to expose the fourth insulator, wherein the second insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen. 2. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulator over a first insulator; forming an oxide semiconductor over the second insulator; forming a third insulator over the oxide semiconductor; forming a resist mask over the third insulator by a lithography method; etching part of the third insulator using the resist mask as an etching mask to form, in the third insulator, an opening portion for exposing a top surface of the oxide semiconductor; forming a first conductor over the third insulator and the exposed top surface of the oxide semiconductor; forming a second conductor over the first conductor; polishing the second conductor and the first conductor to expose the third insulator; etching the exposed portion of the third insulator; etching the oxide semiconductor and the second insulator using the first conductor and the second conductor as an etching mask until the first insulator is exposed; forming a fourth insulator over the first insulator, the first conductor, and the second conductor; forming, in the fourth insulator, an opening portion for exposing the second conductor; forming, in the second conductor, an opening portion for exposing the first conductor to divide the second conductor into a first conductor layer and a second conductor layer; forming, in the first conductor, an opening portion for exposing the oxide semiconductor to divide the first conductor into a third conductor layer and a fourth conductor layer; forming a fifth insulator over the fourth insulator and the oxide semiconductor; forming a sixth insulator over the fifth insulator; forming a third conductor over the sixth insulator; and polishing the third conductor, the sixth insulator, and the fifth insulator to expose the fourth insulator, wherein the second insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen. 3. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulator over a first insulator; forming an oxide semiconductor over the second insulator; forming a first conductor over the oxide semiconductor; forming a third insulator over the first conductor; forming a resist mask over the third insulator by a lithography method; etching part of the third insulator using the resist mask as an etching mask to form, in the third insulator, an opening portion for exposing a top surface of the first conductor; forming a second conductor over the third insulator and at least the exposed top surface of the first conductor; polishing the second conductor to expose the third insulator; etching the exposed portion of the third insulator and part of the first conductor; etching the oxide semiconductor and the second insulator using the first conductor and the second conductor as an etching mask until the first insulator is exposed; forming a fourth insulator over the first insulator and the second conductor; forming, in the fourth insulator, an opening portion for exposing the second conductor; forming, in the second conductor, an opening portion for exposing the first conductor to divide the second conductor into a first conductor layer and a second conductor layer; forming, in the first conductor, an opening portion for exposing the oxide semiconductor to divide the first conductor into a third conductor layer and a fourth conductor layer; forming a fifth insulator over the fourth insulator and the oxide semiconductor; forming a third conductor over the fifth insulator; and polishing the third conductor and the fifth insulator to expose the fourth insulator, wherein the second insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen. 4. A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulator over a first insulator; forming an oxide semiconductor over the second insulator; forming a first conductor over the oxide semiconductor; forming a third insulator over the first conductor; forming a resist mask over the third insulator by a lithography method; etching part of the third insulator using the resist mask as an etching mask to form, in the third insulator, an opening portion for exposing a top surface of the first conductor; forming a second conductor over the third insulator and at least the exposed top surface of the first conductor; polishing the second conductor to expose the third insulator; etching the exposed portion of the third insulator and part of the first conductor; etching the oxide semiconductor and the second insulator using the first conductor and the second conductor as an etching mask until the first insulator is exposed; forming a fourth insulator over the first insulator and the second conductor; forming, in the fourth insulator, an opening portion for exposing the second conductor; forming, in the second conductor, an opening portion for exposing the first conductor to divide the second conductor into a first conductor layer and a second conductor layer; forming, in the first conductor, an opening portion for exposing the oxide semiconductor to divide the first conductor into a third conductor layer and a fourth conductor layer; forming a fifth insulator over the fourth insulator and the oxide semiconductor; forming a sixth insulator over the fifth insulator; forming a third conductor over the sixth insulator; and polishing the third conductor, the sixth insulator, and the fifth insulator to expose the fourth insulator, wherein the second insulator comprises at least one of main constituent elements of the oxide semiconductor other than oxygen.

Assignees

Inventors

Classifications

  • Chemical treatments · CPC title

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • of inorganic materials · CPC title

  • Dry etching; Plasma etching; Reactive-ion etching · CPC title

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Frequently asked questions

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What does patent US9773919B2 cover?
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconduct…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L29/7869. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).