Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-9954003-B2
Application number	US-201715430746-A
Country	US
Kind code	B2
Filing date	Feb 13, 2017
Priority date	Feb 17, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor; and
a first insulating layer,
wherein the first transistor comprises a first electrode, a second electrode, a third electrode, a fourth electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first layer, and a second layer, and a second insulating layer,
wherein the second transistor comprises a fifth electrode, a sixth electrode, a seventh electrode, an eighth electrode, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer, a seventh semiconductor layer, an eighth semiconductor layer, a third layer, a fourth layer, and a third insulating layer,
wherein the first insulating layer comprises a region overlapping with the first electrode,
wherein the first semiconductor layer comprises a region overlapping with the first insulating layer,
wherein the second semiconductor layer comprises a region overlapping with the first semiconductor layer,
wherein the second semiconductor layer comprises a region overlapping with the second electrode and a region overlapping with the third electrode,
wherein the first layer comprises a region overlapping with the second electrode,
wherein the second layer comprises a region overlapping with the third electrode,
wherein the third semiconductor layer comprises a region overlapping with the second semiconductor layer,
wherein the second insulating layer comprises a region overlapping with the third semiconductor layer,
wherein the fourth electrode comprises a region overlapping with the second insulating layer,
wherein a side surface of the fourth electrode and the third semiconductor layer partly overlap with each other with the second insulating layer therebetween,
wherein the first electrode and the fourth electrode partly overlap with each other with the second semiconductor layer therebetween,
wherein the first insulating layer comprises a region overlapping with the fifth electrode,
wherein the fourth semiconductor layer comprises a region overlapping with the first insulating layer,
wherein the sixth semiconductor layer comprises a region overlapping with the fourth semiconductor layer,
wherein the sixth electrode comprises a region overlapping with the sixth semiconductor layer,
wherein the third layer comprises a region overlapping with the sixth electrode,
wherein the fifth semiconductor layer comprises a region overlapping with the first insulating layer,
wherein the seventh semiconductor layer comprises a region overlapping with the fifth semiconductor layer,
wherein the seventh electrode comprises a region overlapping with the seventh semiconductor layer,
wherein the fourth layer comprises a region overlapping with the seventh electrode,
wherein the eighth semiconductor layer comprises a region overlapping with the sixth semiconductor layer and a region overlapping with the seventh semiconductor layer,
wherein the third insulating layer comprises a region overlapping with the eighth semiconductor layer,
wherein the eighth electrode comprises a region overlapping with the third insulating layer,
wherein a side surface of the eighth electrode and the eighth semiconductor layer partly overlap with each other with the third insulating layer therebetween, and
wherein the fifth electrode and the eighth electrode partly overlap with each other with the eighth semiconductor layer therebetween.

2. The semiconductor device according to claim 1 , wherein the first to eighth semiconductor layers each comprise an oxide semiconductor.

3. The semiconductor device according to claim 1 , wherein the first to fourth layers each comprise an oxide semiconductor.

4. The semiconductor device according to claim 1 , wherein at least one of the first electrode and the fourth electrode is capable of functioning as a gate electrode.

5. The semiconductor device according to claim 1 , wherein at least one of the fifth electrode and the eighth electrode is capable of functioning as a gate electrode.

6. The semiconductor device according to claim 1 , wherein a channel is formed in the second semiconductor layer.

7. The semiconductor device according to claim 1 , wherein a channel is formed in the eighth semiconductor layer.

8. The semiconductor device according to claim 1 , wherein a threshold voltage of the second transistor when the fifth electrode and the eighth electrode have a same potential is higher than a threshold voltage of the first transistor when the first electrode and the fourth electrode have a same potential.

9. An electronic device comprising:
the semiconductor device according to claim 1 ; and
an antenna, a battery, an operation switch, a microphone, or a speaker.

10. A semiconductor wafer comprising:
more than one semiconductor device according to claim 1 ; and
a separation region defining each of the semiconductor devices.

11. A semiconductor device comprising:
a first transistor; and
a first insulating layer comprising a first opening, the first insulating layer partly overlapping with and surrounding the first transistor,
wherein the first transistor comprises:
a pair of first oxide semiconductor layers each having an inner side surface facing each other;
a first electrode over one of the pair of first oxide semiconductor layers;
a second electrode over the other of the pair of first oxide semiconductor layers;
a second oxide semiconductor layer in contact with the inner side surfaces of the pair of first oxide semiconductor layers;
a first gate insulating layer over the second oxide semiconductor layer; and
a first gate electrode over the first gate insulating layer,

wherein the second oxide semiconductor layer is in contact with an inner wall of the first opening, and
wherein at least part of the first gate insulating layer and part of the first gate electrode are each in the first opening.

12. The semiconductor device according to claim 11 , wherein a bandgap of the second oxide semiconductor layer is larger than a bandgap of the pair of first oxide semiconductor layers.

13. The semiconductor device according to claim 11 , wherein the first transistor comprises a third oxide semiconductor layer under and in contact with the pair of first oxide semiconductor layers.

14. The semiconductor device according to claim 13 , wherein the second oxide semiconductor layer is in contact with an upper surface of the third oxide semiconductor layer.

15. The semiconductor device according to claim 11 ,
wherein the first transistor comprises a pair of third oxide semiconductor layers under the pair of first oxide semiconductor layers,
wherein the pair of third oxide semiconductor layers each have a side surface facing each other, and
wherein the second oxide semiconductor layer is in contact with the inner side surfaces of the pair of third oxide semiconductor layers.

16. The semiconductor device according to claim 11 , comprising a second transistor,
wherein the first insulating layer comprises a second opening and partly overlaps with and surrounds the second transistor,
wherein the second transistor comprises:
a fourth oxide semiconductor layer;
a third electrode and a fourth electrode over the fourth oxide semiconductor layer, the third electrode and the fourth electrode have side surfaces facing each other;
a fifth oxide semiconductor layer in contact with the side surfaces of the third electrode and the fourth electrode, an upper surface of the fourth oxide semiconductor layer, and an inner wall of the second openi

Assignees

• Semiconductor Energy Lab

Inventors

• Matsuda Shinpei
• Sakakura Masayuki
• Hata Yuki
• Nagatsuka Shuhei
• Endo Yuta
• Yamazaki Shunpei

Classifications

• H01L27/1237

  Electricity · mapped topic

• H01L29/78648

  Electricity · mapped topic

• H01L27/1222 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic